Xilinx XAPP169, Примечание к применению

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22 www.xilinx.com XAPP169 (v1.0) November 24, 1999
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MP3 NG: A Next Generation Consumer Platform
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Software support required for this block consists of the FLASH BIOS which implements low
level primitives for programming, erasing, and checking validity of memory blocks.
IRDA Controller
The IRDA controller is essentially a specialized, fixed function UART. The separate, 2-word,
transmit and receive FIFOs reduce the interrupt overhead associated with data transmission.
At the maximum data rate that the IR transceiver can support (115 kb/s) the CPU will get an
interrupt every 557 ms. (See
Figure 21 .)
.
Table 4: FLASH Controller Interface Signal Summary
Signal Type Description
FL_CE_N[3:0] Output Device chip enables, active Low.
FL_ALE Output Address latch enable.
FL_WE_N Output Write enable, write data is latched on the rising edge.
FL_RE_N Output Read enable, when Low enables device data output buffers.
FL_SE_N Output Enable spare area when Low.
FL_WP_N Output Write protect, active Low.
FL_R/B_N Input Open drain output from devices, pulled Low when a program,
erase, or read operation is in progress.
D_IN[31:0]
32
FIFO
Shift
Register
32
Q D Q D
Bus State
Machine
SYS_CLK
INT_N
RD_IN_N
ACK_N
WR_IN_N[3:0]
32
FIFO
Shift
Register
32
D Q D Q
MUX
IR_TXD
D_OUT[31:0]
Tx State
Machine
IR_RXD
Rx State
Machine
Figure 21: IRDA Controller Block Diagram