Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 363
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
User Registers
R
Fixed-Point Exception Register (XER)
The fixed-point exception register (XER) is a 32-bit register that reflects the result of
arithmetic operations that have resulted in an overflow or carry. This register is also used
to indicate the number of bytes to be transferred by load/store string indexed instructions.
Figure 3-5 shows the format of the XER. The bits in the XER are defined as shown in
Table 3-3 .
The XER is an SPR with an address of 1 (0x001) and can be read and written using the
mfspr and mtspr instructions. The mcrxr instruction can be used to move XER[0:3] into
one of the seven CR fields.
Link Register (LR)
The link register (LR) is a 32-bit register that is used by branch instructions, generally for
the purpose of subroutine linkage. Two types of branch instructions use the link register:
•
Branch-conditional to link-register
( bclr x ) instructions read the branch-target address from
the LR.
• Branch instructions with the link-register update-option enabled load the LR with the
effective address of the instruction following the branch instruction. The link-register
update-option is enabled when the branch-instruction LK opcode field (bit 31) is set
to 1.
The format of LR is shown in Figure 3-6 .
0 1 2 3 24 25 31
SO OV CA TBC
Figure 3-5: Fixed Point Exception Register (XER)
Table 3-3: Fixed Point Exception Register (XER) Bit Definitions
Bit Name Function Description
0 SO Summary overflow
0—No overflow occurred.
1—Overflow occurred.
SO is set to 1 whenever an instruction (except mtspr ) sets the
overflow bit (XER[OV]). Once set, the SO bit remains set until it is
cleared to 0 by an
mtspr instruction (specifying the XER) or an
mcrxr instruction. SO can be cleared to 0 and OV set to 1 using an
mtspr instruction.
1 OV Overflow
0—No overflow occurred.
1—Overflow occurred.
OV can be modified by instructions when the overflow-enable bit
in the instruction encoding is set (OE
=
1). Add, subtract, and negate
instructions set OV
=
1 if the carry out from the result msb is not
equal to the carry out from the result msb + 1. Otherwise, they clear
OV
=
0. Multiply and divide set OV
=
1 if the result cannot be
represented in 32 bits. mtspr can be used to set OV
=
1, and mtspr
and mcrxr can be used to clear OV
=
0.
2 CA Carry
0—Carry did not occur.
1—Carry occurred.
CA can be modified by add-carrying , subtract-from-carrying , add-
extended , and subtract-from-extended instructions. These instructions
set CA
=
1 when there is a carry out from the result msb. Otherwise,
they clear CA
=
0. Shift-right algebraic instructions set CA
=
1 if any 1
bits are shifted out of a negative operand. Otherwise, they clear
CA
=
0. mtspr can be used to set CA
=
1, and mtspr and mcrxr can be
used to clear CA
=
0.
3:24 Reserved
25:31 TBC Transfer-byte count TBC is modified using the mtspr instruction. It specifies the
number of bytes to be transferred by a load-string word indexed
( lswx ) or store-string word indexed ( stswx ) instruction.