Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 851
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Registers
R
Machine-State Register
Several bits within the machine-state register are supported by either PowerPC 40x
processors or PowerPC 6xx/7xx processors, but not both. Others have different meanings
depending on the processor family.
Table E-3 compares these differences.
MMCR n Monitor control registers Performance monitoring
PMC n Performance counters
SIA Sampled instruction address
UMMCR n Monitor control registers (user mode)
UPMC n Performance counters (user mode)
USIA Sampled instruction address (user mode)
ICTC Instruction cache throttling control register Cache control
L2CR L2 cache control register
THRM n Thermal assist unit registers Thermal management
Table E-2: 6xx/7xx Registers Not Supported by 40x Processors
Name Description Purpose
Table E-3: Comparison of MSR Bit Definitions
MSR Bit PowerPC 40x Family PowerPC 6xx/7xx Family
0:5 Reserved Reserved
6 AP—Auxiliary Processor Available
7:11 Reserved
12 APE—APU Exception Enable
13 WE—Wait State Enable POW—Power Management Enable
14 CE—Critical Interrupt Enable Reserved
15 Reserved ILE—Interrupt Little Endian
16 EE—External Interrupt Enable
17 PR—Privilege Level
18 FP—Floating-Point Available
19 ME—Machine-Check Enable
20 FE0—Floating-Point Exception-Mode 0
21 DWE—Debug Wait Enable SE—Single-Step Trace Enable
22 DE—Debug Interrupt Enable BE—Branch Trace Enable
23 FE1—Floating-Point Exception-Mode 1
24 Reserved
25 Reserved IP—Exception Prefix
26 IR—Instruction Relocate
27 DR—Data Relocate
28 Reserved