Xilinx Virtex-II Pro PPC405, Руководство пользователя

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770 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Appendix A: Register Summary
R
Machine-State Register and Condition Register
Table A-3 lists the machine-state and condition registers. These registers are accessed using
special instructions and do not have register numbers associated with them.
Special-Purpose Registers
Table A-4 lists the special-purpose registers sorted by name. The SPRN is the SPR number
that appears in the assembler syntax. The SPRF is the split-field version of the SPRN that
appears in the instruction encoding.
Table A-5, page 772 lists the special-purpose registers
sorted by SPRN and Table A-6, page 773 lists the special-purpose registers sorted by SPRF.
The following notes apply to the “Reset Value” column in these tables:
Notes:
1. The most-recent reset bits are set as follows:
00—No reset occurred. This is the value of WRS if the watchdog timer
did not cause the reset.
01—A processor-only reset occurred.
10—A chip reset occurred.
11—A system reset occurred.
All remaining bits are undefined.
2. WRC is cleared, disabling watchdog time-out resets. All remaining bits are undefined.
Table A-3: Machine-State and Condition Registers
Name Descriptive Name Register Number Privileged Access Reset Value
CR
Condition Register
Not Applicable No Read/Write Undefined
MSR
Machine-State Register
Not Applicable Yes Read/Write 0x0000_0000
Table A-4:
Special-Purpose Registers Sorted by Name
Name Descriptive Name
SPRN SPRF
Privileged Access Reset Value
Dec Hex Hex Binary
CCR0
Core-Configuration Register 0
947 0x3B3 0x27D 0b10011_11101 Yes Read/Write Undefined
CTR Count Register 9 0x009 0x120 0b01001_00000 No Read/Write Undefined
DAC1 Data Address-Compare 1 1014 0x3F6 0x2DF 0b10110_11111 Yes Read/Write Undefined
DAC2 Data Address-Compare 2 1015 0x3F7 0x2FF 0b10111_11111 Yes Read/Write Undefined
DBCR0 Debug-Control Register 0 1010 0x3F2 0x25F 0b10010_11111 Yes Read/Write 0x0000_0000
DBCR1 Debug-Control Register 1 957 0x3BD 0x3BD 0b11101_11101 Yes Read/Write 0x0000_0000
DBSR Debug-Status Register 1008 0x3F0 0x21F 0b10000_11111 Yes Read/Clear Undefined
1
DCCR Data-Cache Cacheability Register 1018 0x3FA 0x35F 0b11010_11111 Yes Read/Write 0x0000_0000
DCWR Data-Cache Write-Through Register 954 0x3BA 0x35D 0b11010_11101 Yes Read/Write Undefined
DEAR Data-Error Address Register 981 0x3D5 0x2BE 0b10101_11110 Yes Read/Write Undefined
DVC1 Data Value-Compare 1 950 0x3B6 0x2DD 0b10110_11101 Yes Read/Write Undefined
DVC2 Data Value-Compare 2 951 0x3B7 0x2FD 0b10111_11101 Yes Read/Write Undefined
ESR Exception-Syndrome Register 980 0x3D4 0x29E 0b10100_11110 Yes Read/Write 0x0000_0000
EVPR Exception-Vector Prefix Register 982 0x3D6 0x2DE 0b10110_11110 Yes Read/Write Undefined
IAC1 Instruction Address-Compare 1 1012 0x3F4 0x29F 0b10100_11111 Yes Read/Write Undefined
IAC2 Instruction Address-Compare 2 1013 0x3F5 0x2B5 0b10101_11111 Yes Read/Write Undefined