Xilinx Virtex-II Pro PPC405, Руководство пользователя

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442 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 5: Memory-System Management
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remaining instructions are received. As instructions are received by the ICU from the PLB,
they are placed in the fill buffer.
The ICU requests the target instruction first, but the order instructions are returned
depends on the design of the PLB device that handles the request (typically a memory
controller). When the ICU receives the target instruction, it is immediately forwarded from
the fill buffer to the instruction queue over the bypass path. The remaining instructions are
received from the PLB and placed in the fill buffer. Subsequent instruction fetches read an
instruction from the fill buffer if it is already present in the buffer. If a cache miss occurred,
the instruction-cacheline is loaded with the fill-buffer contents after all instructions are
received.
Instruction Cacheability Control
Control of instruction cacheability depends on the address-translation mode as follows:
• In real mode, the instruction-cache cacheability register (ICCR) specifies which
physical-memory regions are cacheable. See
Instruction-Cache Cacheability Register
(ICCR) , page 454 , for more information.
• In virtual mode, the storage-attribute fields in the page-translation look-aside buffer
entry (TLB entry) specify which virtual-memory regions are cacheable. See
Storage-
Attribute Fields , page 478 , for more information.
After a processor reset, the processor operates in real mode and all physical-memory
regions are marked as non-cacheable (all ICCR bits are cleared to 0). Prior to specifying
memory regions as cacheable, software must invalidate the instruction cache by executing
the
iccci instruction. (see Cache Instructions , page 456 , for information on this
instruction). After the cache is invalidated, the ICCR can be configured.
Core-Configuration Register , page 459 , describes additional software controls that can be
used to manage instruction prefetching from cacheable and non-cacheable memory.
Instruction-Cache Hint Instruction
The PowerPC embedded-environment architecture and PowerPC Book-E architecture
define an
instruction-cache block touch ( icbt ) instruction that can be used to improve
instruction-cache performance. Software uses icbt to indicate that instruction-fetching is
likely to occur from the specified address in the near future. When PLB bandwidth is
available, the processor can prefetch the instruction-cacheline associated with the
icbt
operand address. This instruction executes as a no-operation if loading the cacheline
results in a page-translation exception or a protection exception.
Instruction-Cache Synonyms
NOTE: The following information applies only if instruction address translation is enabled.
Proper cache operation depends on a physical address being cached by at most one
cacheline. An instruction-cache
synonym exists when a single physical address is cached by
multiple instruction-cachelines. This can occur when software uses page translation to
map multiple virtual addresses to the same physical address. Cache synonyms pose
serious problems for system software when managing memory-access protection, page
translation, and coherency.
In the PPC405, the instruction cache is physically tagged and virtually indexed. When
translation is enabled, the physical address is translated from the virtual address. A
synonym can exist when common bit ranges in the virtual address and physical address
are used to access the cache. This occurs when bits in the virtual index are involved in
translating physical-tag bits.
To illustrate the problem, assume 4 KB page translation maps two virtual addresses,
0x8888_8000 and 0xFFFF_F000, to the same physical address, 0x4444_4000 (see
Chapter 6,
Virtual-Memory Management for information on address translation). When a 4 KB page
address is translated, the translation mechanism maps each effective-page number (EA
0:19
)