Xilinx Virtex-II Pro PPC405, Руководство пользователя

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440 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 5: Memory-System Management
R
Figure 5-4 shows an example of how the physical-address fields are used to select a data
operand from the data-cache array. The instruction cache operates in a similar manner,
using fields from both the physical address and the effective address.
Referring to Figure 5-4 , the line field in the data address is used to select a congruence class
from the cache array. The congruence class contains two lines, one from each way. Each line
contains a tag, meaning two tags are present in a congruence class. The tag field in the data
address is compared to both tags in the congruence class. A
hit occurs when the data-
address tag field is equal to one of the two tags. A miss occurs when the data-address tag
field is not equal to either of the tags.
Figure 5-3: Address Fields Used to Access Caches
UG011_35_033101
Data
Physical Address
0 27 19 31
Tag Line Byte
0 27 19 31
Line Byte
Instruction
Physical Address
0 22 31
Tag
Instruction
Effective Address
Figure 5-4: Data-Cache Access Example
UG011_36_100901
Way A
Tag
LRU &
Dirty
Data
Way B
Tag Data
Equal
?
Equal
?
Select
Data Operand
Tag Line Byte
Yes
(Hit)
Yes (Hit)
No
(Miss)
No
(Miss)
Congruence
Class
32-Byte Data Cacheline Buffer
LRU &
Dirty
Data Address
0 18
0 Physical 31 26, 27 18,19
0 18 0 32*8 0 32*8
0 32*8