Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 437
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
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Chapter 5
Memory-System Management
This chapter describes how software can manage the interaction between the PPC405
processor and the memory system. Memory-system management includes cache control,
the use of storage attributes, and memory-coherency considerations. The virtual-memory
environment is described separately in
Chapter 6, Virtual-Memory Management .
Memory-System Organization
Figure 5-1 shows the memory-system organization supported by the PPC405. The
processor implements separate internal instruction and data caches, an architectural
construct known as the
Harvard cache model . The PPC405 does not provide hardware
support for attachment of a level-2 (L2) or higher caches. The processor communicates
with system memory over the processor local bus (PLB), usually through a memory
controller.
The PowerPC architecture does not define the type, organization, implementation, or
existence of internal or external caches. The cache structure of other PowerPC processors
can differ from that implemented by the PPC405. To maximize portability, software that
operates on multiple PowerPC implementations should always assume implemenation of
a Harvard cache model.
Separate instruction and data on-chip-memory (OCM) can be attached to the PPC405 cache
controllers using a dedicated processor interface. The performance of OCM accesses can be
identical to that of a cache hit, depending on how much block RAM (BRAM) is connected
to the processor through the OCM controllers. Refer to the
PPC405 Processor Block
Manual for more information on the OCM and OCM controllers.
Figure 5-1: PPC405 Memory-System Organization
UG011_42_021902
Processor
Memory
Controller
System
Memory
Processor
Local Bus
I-Cache
Controller
I-Cache
Array
Instruction-Cache
Unit
Instruction
OCM
D-Cache
Array
D-Cache
Controller
Data-Cache
Unit
Data
OCM
Execute GPRs