Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 419
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Multiply-Accumulate Instruction-Set Extensions
R
Figure 3-33 shows the operation of the negative multiply-accumulate low-halfword to
word instructions.
Multiply Halfword to Word Instructions
Multiply Cross-Halfword to Word Instructions
Table 3-46 shows the PPC405 multiply cross-halfword to word instructions. These instructions
take the lower halfword of the first source operand ( r A[16:31]) and multiply it with the
upper halfword of the second source operand ( r B[0:15]), producing a 32-bit product. The
product is signed or unsigned, depending on the instruction.
For each type of instruction shown in Table 3-46 , the “Operation” column indicates the
multiply operation performed. The column also shows, on an instruction-by-instruction
basis, how the CR register is updated (if at all). The XER register is not updated by these
instructions.
Figure 3-33: Negative Multiply-Accumulate Low-Halfword to Word Operation
UG011_25_033101
r D
0 31
0 32
r A
0 31 16
r B
0 31 15
×
r D
0 31
+
Intermediate Result
−
1
1
Table 3-46: Multiply Cross-Halfword to Word Instructions
Mnemonic Name Operation
Operand
Syntax
Multiply Cross-Halfword to Word Signed Instructions
r D is loaded with the signed product ( r A[16:31])
×
( r B[0:15]).
mulchw Multiply Cross Halfword to Word
Signed
CR0 is
not
updated.
r D, r A, r B
mulchw.
Multiply Cross Halfword to Word
Signed and Record
CR0 is updated to reflect the result.