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VC7203 GTX Transceiver Characterization Board

www.xilinx.com

UG957 (v1.3) October 17, 2014

Appendix C

Master Constraints File Listing

The master Xilinx design constraints (XDC) file template for the VC7203 board provides
for designs targeting the VC7203 Virtex®-7 FPGA GTX Transceiver Characterization
Board. Net names in the listed constraints correlate with net names on the VC7203 board
schematic. Users must identify the appropriate pins and replace the net names below with
net names in the user RTL. See

Vivado Design Suite User Guide: Using Constraints

(UG903)

[Ref 5]

for more information.

Note:

Visit the

Virtex-7 FPGA VC7203 Characterization Kit support page

for the latest XDC file.

VC7203 Board XDC Listing

#FMC1

set_property PACKAGE_PIN AM38 [get_ports FMC1_PRSNT_M2C_L]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_PRSNT_M2C_L]

set_property PACKAGE_PIN AJ32 [get_ports FMC1_CLK0_M2C_P]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK0_M2C_P]

set_property PACKAGE_PIN AK32 [get_ports FMC1_CLK0_M2C_N]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK0_M2C_N]

set_property PACKAGE_PIN AL31 [get_ports FMC1_CLK1_M2C_P]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK1_M2C_P]

set_property PACKAGE_PIN AL32 [get_ports FMC1_CLK1_M2C_N]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK1_M2C_N]

set_property PACKAGE_PIN AD32 [get_ports FMC1_CLK2_BIDIR_P]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK2_BIDIR_P]

set_property PACKAGE_PIN AD33 [get_ports FMC1_CLK2_BIDIR_N]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK2_BIDIR_N]

set_property PACKAGE_PIN AC34 [get_ports FMC1_CLK3_BIDIR_P]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK3_BIDIR_P]

set_property PACKAGE_PIN AD35 [get_ports FMC1_CLK3_BIDIR_N]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_CLK3_BIDIR_N]

#FMC1 LA

set_property PACKAGE_PIN AU38 [get_ports FMC1_LA00_CC_P]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA00_CC_P]

set_property PACKAGE_PIN AV38 [get_ports FMC1_LA00_CC_N]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA00_CC_N]

set_property PACKAGE_PIN AU39 [get_ports FMC1_LA01_CC_P]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA01_CC_P]

set_property PACKAGE_PIN AV39 [get_ports FMC1_LA01_CC_N]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA01_CC_N]

set_property PACKAGE_PIN AN38 [get_ports FMC1_LA02_P]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA02_P]

set_property PACKAGE_PIN AP38 [get_ports FMC1_LA02_N]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA02_N]

set_property PACKAGE_PIN AM41 [get_ports FMC1_LA03_P]

set_property IOSTANDARD LVCMOS18 [get_ports FMC1_LA03_P]

Send Feedback

Содержание Virtex-7 VC7203

Страница 1: ...VC7203 Virtex 7 FPGA GTX Transceiver Characterization Board User Guide UG957 v1 3 October 17 2014...

Страница 2: ...erms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and...

Страница 3: ...n 15 PROG_B Pushbutton 17 DONE LED 17 INIT LED 17 System ACE Tool SD Controller 17 System ACE Tool SD Controller Reset 17 System ACE Tool SD Configuration Address DIP Switches 17 200 MHz 2 5V LVDS Osc...

Страница 4: ...ization Board UG957 v1 3 October 17 2014 Solution Centers 73 References 73 Appendix E Regulatory and Compliance Information Declaration of Conformity 75 Directives 75 Standards 75 Electromagnetic Comp...

Страница 5: ...G1761 packages However certain interfaces that are available in larger density devices might not be available in the XC7VX485T device for example GTX QUAD_111 GTX QUAD_112 FMC 3 and so on VC7203 Board...

Страница 6: ...Figure 1 1 Figure 1 1 VC7203 Board Block Diagram UG957_c1_01_120213 FPGA Power Source Onboard Regulation Board Utility Power Onboard Regulation Pushbuttons DIP Switches and LEDs SuperClock 2 Module I...

Страница 7: ...transceiver connector pads Q111 Q112 Q113 Q114 Q115 Q116 Q117 Q118 and Q119 page 22 5 U8 USB JTAG connector micro B receptacle page 15 6 J7 JTAG connector alternate access for programming cables page...

Страница 8: ...atus LEDS for FPGA logic transceiver and utility power 17 J199 J200 J201 J202 J203 J204 Power regulation jumpers for onboard regulators 18 J28 J29 J31 J32 J33 J34 J35 J36 J37 J40 J104 J105 J106 J107 J...

Страница 9: ...J29 and J28 provide no reverse polarity protection use a power supply with a current limit set at 6A max Caution Do NOT apply 12V power to more than a single input source For example do not apply pow...

Страница 10: ...FC U9 Switching Regulators 2 Phases 1 0V at 40A max U5 U51 Switching Regulator 1 8V at 10A max U56 Switching Regulator 1 0V at 10A max Switching Regulator 1 8V at 10A max U6 Power Controller 2 UCD9248...

Страница 11: ...6V VCCO_HR 1 8V default Utility PTH12060W U2 Fixed switching regulator 10A UTIL_5V0 5 0V PTH12020W U13 Fixed switching regulator 18A UTIL_3V3 3 3V PTH12020W U52 Fixed switching regulator 18A UTIL_2V5...

Страница 12: ...Appendix A Default Jumper Settings Monitoring Voltage and Current Voltage and current monitoring and control are available for FPGA logic and transceiver power rails through Texas Instruments Fusion D...

Страница 13: ...ncluded with the VC7203 board Each GTX transceiver rail comes with an associated jack that can be used to provide external power These external supply jacks are shown in Table 1 3 Caution The 7 series...

Страница 14: ...ns are detailed in Table 1 5 Figure 1 6 shows the heatsink fan power connector J121 X Ref Target Figure 1 5 Figure 1 5 Active FPGA Heatsink Table 1 5 Fan Power Connections Fan Wire Header Pin Black J1...

Страница 15: ...2 System ACE tool SD callout 7 Figure 1 2 JTAG cable connector callout 6 Figure 1 2 The VC7203 board comes with an embedded USB to JTAG configuration module U8 which allows a host computer to access t...

Страница 16: ...in J1 jumper OFF Installing the J1 jumper adds the FMC interfaces as well X Ref Target Figure 1 7 Figure 1 7 JTAG Chain UG957_c1_07_100712 FMC1_PRSNT_M2C_L FMC2_PRSNT_M2C_L FMC1 HPC Connector TDI TDO...

Страница 17: ...ion files on an SD card These configuration files can be used to program the FPGA The SD card connects to the SD card connector J211 callout 7 Figure 1 2 located directly below the System ACE SD contr...

Страница 18: ...are connected to the SMA connectors as shown in Table 1 8 Table 1 6 SW8 DIP Switch Configuration Configuration Bitstream Address ADR2 ADR1 ADR0 0 ON ON ON 1 ON ON OFF 2 ON OFF ON 3 ON OFF OFF 4 OFF ON...

Страница 19: ...11 Clock Recovery Output BA1 Clock Recovery Output LVDS CM_LVDS3_P 17 Clock Recovery Input BB1 Clock Recovery Output LVDS CM_LVDS3_N 19 Clock Recovery Input K19 Regional Clock Input LVDS_25 CM_GCLK_P...

Страница 20: ...utput LVCMOS18 CM_CTRL_17 95 CS0_C3A Input D18 Control I O Output LVCMOS18 CM_CTRL_18 97 CS1_C4A Input D17 Control I O In Out LVCMOS18 CM_CTRL_19 99 NC F20 Control I O In Out LVCMOS18 CM_CTRL_20 101 N...

Страница 21: ...Standard E42 User Switch Input LVCMOS18 USER_SW1 1 2 C40 User Switch Input LVCMOS18 USER_SW2 2 4 C41 User Switch Input LVCMOS18 USER_SW3 3 6 H40 User Switch Input LVCMOS18 USER_SW4 4 8 H41 User Switc...

Страница 22: ...connect to pins on the XCVX485T Note Figure 1 10 is for reference only and might not reflect the current revision of the board Each GTX Quad and its associated reference clocks CLK0 and CLK1 are brou...

Страница 23: ...1_RX0_P 111 J84 2 149 BB7 111_RX0_N 111 J84 2 148 BA2 111_TX1_P 111 J84 1 808 BA1 111_TX1_N 111 J84 1 808 BA6 111_RX1_P 111 J84 1 855 BA5 111_RX1_N 111 J84 1 855 AY4 111_TX2_P 111 J84 2 097 AY3 111_TX...

Страница 24: ...5 AP8 112_RX3_P 112 J85 3 365 AP7 112_RX3_N 112 J85 3 365 AP4 113_TX0_P 113 J86 2 949 AP3 113_TX0_N 113 J86 2 949 AN6 113_RX0_P 113 J86 3 243 AN5 113_RX0_N 113 J86 3 243 AN2 113_TX1_P 113 J86 2 736 AN...

Страница 25: ...571 AD4 114_RX3_P 114 J158 2 570 AD3 114_RX3_N 114 J158 2 570 Y2 115_TX0_P 115 J83 2 805 Y1 115_TX0_N 115 J83 2 806 AA4 115_RX0_P 115 J83 2 898 AA3 115_RX0_N 115 J83 2 898 V2 115_TX1_P 115 J83 2 525 V...

Страница 26: ...2 555 M6 116_RX3_P 116 J84 2 821 M5 116_RX3_N 116 J84 2 821 K2 117_TX0_P 117 J85 2 617 K1 117_TX0_N 117 J85 2 616 K6 117_RX0_P 117 J85 2 886 K5 117_RX0_N 117 J85 2 886 J4 117_TX1_P 117 J85 2 400 J3 1...

Страница 27: ...118 J86 3 044 A8 118_RX3_P 118 J86 3 515 A7 118_RX3_N 118 J86 3 515 E2 119_TX0_P 119 J163 2 570 E1 119_TX0_N 119 J163 2 570 D8 119_RX0_P 119 J163 2 677 D7 119_RX0_N 119 J163 2 677 D4 119_TX1_P 119 J16...

Страница 28: ...LK1_P 112 J85 AU9 112_REFCLK1_N 112 J85 AH8 113_REFCLK0_P 113 J86 AH7 113_REFCLK0_N 113 J86 AK7 113_REFCLK1_N 113 J86 AK8 113_REFCLK1_P 113 J86 AD8 114_REFCLK0_P 114 J158 AD7 114_REFCLK0_N 114 J158 AF...

Страница 29: ...CP2103 are listed in Table 1 16 A10 119_REFCLK0_P 119 J163 A9 119_REFCLK0_N 119 J163 C10 119_REFCLK1_P 119 J163 C9 119_REFCLK1_N 119 J163 Table 1 14 GTX Transceiver Reference Clock Inputs Cont d U1 F...

Страница 30: ...57 1 FPGA Mezzanine card FMC specification The FMC HPC connector is a 10 x 40 position socket See Appendix B VITA 57 1 FMC Connector Pinouts for a cross reference of signal names to pin coordinates F...

Страница 31: ...able 1 18 VITA 57 1 FMC1 HPC Connections at JA2 U1 FPGA Pin Net Name FMC Pin AJ32 FMC1_CLK0_M2C_P H4 AK32 FMC1_CLK0_M2C_N H5 AL31 FMC1_CLK1_M2C_P G2 AL32 FMC1_CLK1_M2C_N G3 AD32 FMC1_CLK2_BIDIR_P K4 A...

Страница 32: ...A30 FMC1_HA15_N F17 AB29 FMC1_HA16_P E15 AC29 FMC1_HA16_N E16 AB33 FMC1_HB00_CC_P K25 AC33 FMC1_HB00_CC_N K26 AF35 FMC1_HB01_P J24 AF36 FMC1_HB01_N J25 AE37 FMC1_HB02_P F22 AF37 FMC1_HB02_N F23 AF34 F...

Страница 33: ...HB15_P J33 AE30 FMC1_HB15_N J34 Y32 FMC1_HB16_P F34 Y33 FMC1_HB16_N F35 AU38 FMC1_LA00_CC_P G6 AV38 FMC1_LA00_CC_N G7 AU39 FMC1_LA01_CC_P D8 AV39 FMC1_LA01_CC_N D9 AN38 FMC1_LA02_P H7 AP38 FMC1_LA02_N...

Страница 34: ...38 FMC1_LA14_N C19 BB38 FMC1_LA15_P H19 BB39 FMC1_LA15_N H20 BA39 FMC1_LA16_P G18 BA40 FMC1_LA16_N G19 AK34 FMC1_LA17_CC_P D20 AL34 FMC1_LA17_CC_N D21 AJ33 FMC1_LA18_CC_P C22 AK33 FMC1_LA18_CC_N C23 A...

Страница 35: ...A31_N G34 AL29 FMC1_LA32_P H37 AL30 FMC1_LA32_N H38 AH29 FMC1_LA33_P G36 AH30 FMC1_LA33_N G37 AM38 FMC1_PRSNT_M2C_L H2 Table 1 19 VITA 57 1 FMC1 HPC Connections at JA3 U1 FPGA Pin Net Name FMC Pin E34...

Страница 36: ...9 G37 FMC2_HA07_N J10 F39 FMC2_HA08_P F10 E39 FMC2_HA08_N F11 J37 FMC2_HA09_P E9 J38 FMC2_HA09_N E10 H38 FMC2_HA10_P K13 G38 FMC2_HA10_N K14 J36 FMC2_HA11_P J12 H36 FMC2_HA11_N J13 P25 FMC2_HA12_P F13...

Страница 37: ...3 FMC2_HB07_P J27 G23 FMC2_HB07_N J28 G28 FMC2_HB08_P F28 G29 FMC2_HB08_N F29 K28 FMC2_HB09_P E27 J28 FMC2_HB09_N E28 H28 FMC2_HB10_P K31 H29 FMC2_HB10_N K32 K27 FMC2_HB11_P J30 J27 FMC2_HB11_N J31 M2...

Страница 38: ...6_P C10 M34 FMC2_LA06_N C11 H34 FMC2_LA07_P H13 H35 FMC2_LA07_N H14 K29 FMC2_LA08_P G12 K30 FMC2_LA08_N G13 J30 FMC2_LA09_P D14 H30 FMC2_LA09_N D15 L29 FMC2_LA10_P C14 L30 FMC2_LA10_N C15 J31 FMC2_LA1...

Страница 39: ...LA22_N G25 C38 FMC2_LA23_P D23 C39 FMC2_LA23_N D24 B37 FMC2_LA24_P H28 B38 FMC2_LA24_N H29 E32 FMC2_LA25_P G27 D32 FMC2_LA25_N G28 B32 FMC2_LA26_P D26 B33 FMC2_LA26_N D27 E33 FMC2_LA27_P C26 D33 FMC2_...

Страница 40: ...C3_CLK2_BIDIR_N K5 J13 FMC3_CLK3_BIDIR_P J2 H13 FMC3_CLK3_BIDIR_N J3 AU14 FMC3_HA00_CC_P F4 AU13 FMC3_HA00_CC_N F5 AV13 FMC3_HA01_CC_P E2 AW13 FMC3_HA01_CC_N E3 AW12 FMC3_HA02_P K7 AY12 FMC3_HA02_N K8...

Страница 41: ..._HA15_N F17 G14 FMC3_HB00_CC_P K25 G13 FMC3_HB00_CC_N K26 F16 FMC3_HB01_P J24 E15 FMC3_HB01_N J25 E14 FMC3_HB02_P F22 E13 FMC3_HB02_N F23 H16 FMC3_HB03_P E21 G16 FMC3_HB03_N E22 G12 FMC3_HB04_P F25 F1...

Страница 42: ...AR14 FMC3_LA01_CC_P D8 AT14 FMC3_LA01_CC_N D9 AJ16 FMC3_LA02_P H7 AJ15 FMC3_LA02_N H8 AK14 FMC3_LA03_P G9 AK13 FMC3_LA03_N G10 AK15 FMC3_LA04_P H10 AL14 FMC3_LA04_N H11 AJ13 FMC3_LA05_P D11 AJ12 FMC3...

Страница 43: ...17_CC_N D21 AU18 FMC3_LA18_CC_P C22 AV18 FMC3_LA18_CC_N C23 AL19 FMC3_LA19_P H22 AM19 FMC3_LA19_N H23 AK17 FMC3_LA20_P G21 AL17 FMC3_LA20_N G22 AM18 FMC3_LA21_P H25 AM17 FMC3_LA21_N H26 AK19 FMC3_LA22...

Страница 44: ...on VCCADC is provided by an onboard regulator U43 Analog Devices P N ADP123AUJZ R7 The output voltage of the regulator VCCADC can be adjusted using the potentiometer R233 In addition the VC7203 board...

Страница 45: ...als mapped to FPGA pins E21 and F21 respectively The I2C idcode for the PCA9547 device is 0x70 The bus hosts four components SuperClock 2 module 7 series GTX transceiver power supply module FMC1 FMC2...

Страница 46: ...46 www xilinx com VC7203 GTX Transceiver Characterization Board UG957 v1 3 October 17 2014 Chapter 1 VC7203 Board Features and Operation Send Feedback...

Страница 47: ...mper Comments J4 UTIL_3V3 Upper Left AFX 1 2 J184 UTIL_2V5 Upper Left AFX 1 2 J24 UTIL_5V0 Upper Left AFX 1 2 J78 VTT_HR SOURCE Upper Left GND 1 2 Red 20A jumper J210 PMBUS CTRL Upper Left GND 2 3 J48...

Страница 48: ...48 www xilinx com VC7203 GTX Transceiver Characterization Board UG957 v1 3 October 17 2014 Appendix A Default Jumper Settings Send Feedback...

Страница 49: ...N GND GND DP3_C2M_P DP3_C2M_N GND GND DP4_C2M_P DP4_C2M_N GND GND DP5_C2M_P DP5_C2M_N GND RES1 GND GND DP9_M2C_P DP9_M2C_N GND GND DP8_M2C_P DP8_M2C_N GND GND DP7_M2C_P DP7_M2C_N GND GND DP6_M2C_P DP6...

Страница 50: ...50 www xilinx com VC7203 GTX Transceiver Characterization Board UG957 v1 3 October 17 2014 Appendix B VITA 57 1 FMC Connector Pinouts Send Feedback...

Страница 51: ...perty PACKAGE_PIN AL32 get_ports FMC1_CLK1_M2C_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_CLK1_M2C_N set_property PACKAGE_PIN AD32 get_ports FMC1_CLK2_BIDIR_P set_property IOSTANDARD LVCMOS18 g...

Страница 52: ...ports FMC1_LA10_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA10_P set_property PACKAGE_PIN AT40 get_ports FMC1_LA10_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA10_N set_property PACKAGE...

Страница 53: ...get_ports FMC1_LA24_N set_property PACKAGE_PIN AG33 get_ports FMC1_LA25_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_LA25_P set_property PACKAGE_PIN AH33 get_ports FMC1_LA25_N set_property IOSTA...

Страница 54: ...rts FMC1_HA05_P set_property PACKAGE_PIN BB41 get_ports FMC1_HA05_N set_property IOSTANDARD LVCMOS18 get_ports FMC1_HA05_N set_property PACKAGE_PIN AW41 get_ports FMC1_HA06_P set_property IOSTANDARD L...

Страница 55: ...property PACKAGE_PIN AF34 get_ports FMC1_HB03_P set_property IOSTANDARD LVCMOS18 get_ports FMC1_HB03_P set_property PACKAGE_PIN AG34 get_ports FMC1_HB03_N set_property IOSTANDARD LVCMOS18 get_ports FM...

Страница 56: ...CKAGE_PIN E34 get_ports FMC2_CLK0_M2C_P set_property IOSTANDARD LVCMOS18 get_ports FMC2_CLK0_M2C_P set_property PACKAGE_PIN E35 get_ports FMC2_CLK0_M2C_N set_property IOSTANDARD LVCMOS18 get_ports FMC...

Страница 57: ...MC2_LA10_P set_property PACKAGE_PIN L30 get_ports FMC2_LA10_N set_property IOSTANDARD LVCMOS18 get_ports FMC2_LA10_N set_property PACKAGE_PIN J31 get_ports FMC2_LA11_P set_property IOSTANDARD LVCMOS18...

Страница 58: ...PIN E32 get_ports FMC2_LA25_P set_property IOSTANDARD LVCMOS18 get_ports FMC2_LA25_P set_property PACKAGE_PIN D32 get_ports FMC2_LA25_N set_property IOSTANDARD LVCMOS18 get_ports FMC2_LA25_N set_prope...

Страница 59: ..._HA05_N set_property IOSTANDARD LVCMOS18 get_ports FMC2_HA05_N set_property PACKAGE_PIN Y29 get_ports FMC2_HA06_P set_property IOSTANDARD LVCMOS18 get_ports FMC2_HA06_P set_property PACKAGE_PIN Y30 ge...

Страница 60: ...03_P set_property IOSTANDARD LVCMOS18 get_ports FMC2_HB03_P set_property PACKAGE_PIN H26 get_ports FMC2_HB03_N set_property IOSTANDARD LVCMOS18 get_ports FMC2_HB03_N set_property PACKAGE_PIN G21 get_p...

Страница 61: ...8 get_ports FMC3_CLK0_M2C_P set_property PACKAGE_PIN AY17 get_ports FMC3_CLK0_M2C_N set_property IOSTANDARD LVCMOS18 get_ports FMC3_CLK0_M2C_N set_property PACKAGE_PIN AW18 get_ports FMC3_CLK1_M2C_P s...

Страница 62: ...ts FMC3_LA10_N set_property IOSTANDARD LVCMOS18 get_ports FMC3_LA10_N set_property PACKAGE_PIN AN11 get_ports FMC3_LA11_P set_property IOSTANDARD LVCMOS18 get_ports FMC3_LA11_P set_property PACKAGE_PI...

Страница 63: ...t_ports FMC3_LA25_P set_property PACKAGE_PIN AP17 get_ports FMC3_LA25_N set_property IOSTANDARD LVCMOS18 get_ports FMC3_LA25_N set_property PACKAGE_PIN AP20 get_ports FMC3_LA26_P set_property IOSTANDA...

Страница 64: ..._ports FMC3_HA05_N set_property PACKAGE_PIN AV20 get_ports FMC3_HA06_P set_property IOSTANDARD LVCMOS18 get_ports FMC3_HA06_P set_property PACKAGE_PIN AW20 get_ports FMC3_HA06_N set_property IOSTANDAR...

Страница 65: ...property PACKAGE_PIN F12 get_ports FMC3_HB04_N set_property IOSTANDARD LVCMOS18 get_ports FMC3_HB04_N set_property PACKAGE_PIN K12 get_ports FMC3_HB05_P set_property IOSTANDARD LVCMOS18 get_ports FMC3...

Страница 66: ...CM_CTRL_6 set_property PACKAGE_PIN A17 get_ports CM_CTRL_7 set_property IOSTANDARD LVCMOS18 get_ports CM_CTRL_7 set_property PACKAGE_PIN B21 get_ports CM_CTRL_8 set_property IOSTANDARD LVCMOS18 get_p...

Страница 67: ...PIN H40 get_ports USER_SW4 set_property IOSTANDARD LVCMOS18 get_ports USER_SW4 set_property PACKAGE_PIN H41 get_ports USER_SW5 set_property IOSTANDARD LVCMOS18 get_ports USER_SW5 set_property PACKAGE_...

Страница 68: ...DATA USB_GPIOs set_property PACKAGE_PIN B28 get_ports USB_GPIO_0 set_property IOSTANDARD LVCMOS18 get_ports USB_GPIO_0 set_property PACKAGE_PIN B29 get_ports USB_GPIO_1 set_property IOSTANDARD LVCMOS1...

Страница 69: ...get_ports 112_RX2_N set_property PACKAGE_PIN AU2 get_ports 112_TX1_P set_property PACKAGE_PIN AU1 get_ports 112_TX1_N set_property PACKAGE_PIN AU6 get_ports 112_RX1_P set_property PACKAGE_PIN AU5 get...

Страница 70: ...rty PACKAGE_PIN AA6 get_ports 115_RX2_P set_property PACKAGE_PIN AA5 get_ports 115_RX2_N set_property PACKAGE_PIN AC2 get_ports 115_TX1_P set_property PACKAGE_PIN AC1 get_ports 115_TX1_N set_property...

Страница 71: ...CKAGE_PIN G2 get_ports 118_TX2_P set_property PACKAGE_PIN G1 get_ports 118_TX2_N set_property PACKAGE_PIN F8 get_ports 118_RX2_P set_property PACKAGE_PIN F7 get_ports 118_RX2_N set_property PACKAGE_PI...

Страница 72: ...72 www xilinx com VC7203 GTX Transceiver Characterization Board UG957 v1 3 October 17 2014 Appendix C Master Constraints File Listing Send Feedback...

Страница 73: ...er Record AR 52383 These documents and websites provide supplemental material useful with this guide 1 7 Series FPGAs and Zynq 7000 All Programmable SoC XADC Dual 12 Bit 1 MSPS Analog to Digital Conve...

Страница 74: ...UG470 10 7 Series FPGAs SelectIO Resources User Guide UG471 11 7 Series FPGAs Clocking Resources User Guide UG472 12 7 Series FPGAs Configurable Logic Block User Guide UG474 13 7 Series FPGAs Packagin...

Страница 75: ...Electrotechnical Standardization CENELEC IEC standards are maintained by the International Electrotechnical Commission IEC Electromagnetic Compatibility EN 55022 2010 Information Technology Equipment...

Страница 76: ...quipment WEEE The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste This product complies with Directive 2002 95 EC on th...

Страница 77: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Xilinx CK V7 VC7203 G J CK V7 VC7203 G...

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