Xilinx Virtex-6 FPGA, Руководство по началу работы

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74 www.xilinx.com Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Getting Started with the Virtex-6 FPGA IBERT Reference Design
15. Configure the bit error ratio test (BERT) parameter settings (see Figure 78 ):
a. Set the TX/RX data patterns to PRBS 7-bit and 15-bit.
b. Click the BERT Reset buttons for each channel.
16. View the reported BERT (see Figure 79 ). The RX bit error count should be 0.
Congratulations! The IBERT reference design for the Virtex-6 FPGA Connectivity Kit has
been set up and the pre-built demo that uses the GTX transceivers running at 3.125 Gb/s
has been tested.
For further details on other example reference designs available for the ML605 board, refer
to
http://www.xilinx.com/ml605 and click on ML605 Documentation .
X-Ref Target - Figure 78
Figure 78: Configuring the BERT Settings for the GTX Transceiver Channels
X-Ref Target - Figure 79
Figure 79: Verify the Bit Error Ratio on All Four Transceiver Channels
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