Xilinx Virtex-4 ML455, Руководство пользователя

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32 www.xilinx.com Virtex-4 ML455 PCI/PCI-X Board
UG084 (v1.0) May 17, 2005
Chapter 3: Hardware Description
R
The PCI bus clock for the top mounted socket J1 is created by the FPGA, at pin U10.B17.
This signal SOURCE_SOCKET_CLK is routed to U8 pin 1. U8 is a four-channel PCI clock
buffer device.
Channel OUT1 of U8, on pin 5, is wired to PCI bus clock J1.B16.
There are also two feedback clock traces wired from U8 back to FPGA U10, U8.3 (OUT0),
signal FEEDBACK_SOCKET_CLK_GLOBAL is routed to U10.A17, and U8.8 (OUT3),
signal FEEDBACK_SOCKET_CLK_REGIONAL is routed to U10.D25.
The three clock traces driven from U8 are length matched to enable the FPGA to sense the
clock timing at the J1 PCI socket.
XC2C32 CoolRunner-II CPLD U6
Figure 4-5, page 38 and Table 4-4, page 40 summarize the CPLD connections to:
•
U1: XCF32PFSG48C Platform Flash configuration device
•
U10: XC4VLX25 FPGA Bank 1
•
U10: XC4VLX25 FPGA Bank 0 Configuration I/F
•
P3: Configuration Image select header
•
SW6 (PROG), SW7: General purpose push-button switches
All XC2C32 I/O are 2.5V, and the XC2C32 V
CCINT
is 1.8V. Chapter 4, “Configuration,”
includes more details concerning the ML455 board configuration.
XCF32PFS48C Platform Flash U1
Figure 4-5, page 38 and Table 4-5, page 41 summarize the Platform Flash connections to
the XC4VLX25 FPGA U10 and the XC2C32 CPLD U6.
The XCF32PFS48C V
CCO
is 2.5V.
The Platform Flash holds up to four configuration images for the XC4VLX25 FPGA. As
shown in
Figure 4-5 , the configuration image is selected by applying shorting blocks to
header P3.
In concert with the XC2C32 CPLD, the XCF32PFS48C supports static and dynamic
reconfiguration of the FPGA.
Chapter 4, “Configuration,” provides more details
concerning the ML455 board configuration.
A92 unused B92 unused
A93 GND B93 unused
A94 unused B94 GND
Table 3-12: J1 PCI Socket Pinout (Continued)
J1 A Side Signal J1 B Side Signal
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