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VCU110 Evaluation Board
25
UG1073 (v1.2) March 26, 2016
Chapter 1:
VCU110 Evaluation Board Features
The connections between the dual Quad SPI components U182, U183 and XCVU190 banks
0 and 65 are listed in
.
Hybrid Memory Cube
[
, callout 7]
The HMC component memory system is comprised of one 16-lane 4 GB device (Micron
MT43A4G80100) located at U160. This memory system is connected to the XCVU190 MGTH
banks 225-232 (8 MGTH Quads).
Table 1-7:
Dual-QSPI Memory U182, U183 I/F to FPGA U1 Banks 0 and 65
FPGA (U1)
Pin
Schematic Net
Name
I/O Standard
QSPI Memory
Pin Number
Pin Name
Reference
Designator
AM14
QSPI0_IO0
D3
DQ0
U182
AK14
QSPI0_IO1
D2
DQ1
U182
AF16
QSPI0_IO2
C4
DQ2_W_B
U182
AH14
QSPI0_IO3
D4
DQ3_HOLD_B
U182
AF14
QSPI0_CS_B
C2
S_B
U182
AB16
FPGA_CCLK
B2
C
U182
BE19
QSPI1_IO0
LVCMOS18
D3
DQ0
U183
BF19
QSPI1_IO1
LVCMOS18
D2
DQ1
U183
BD18
QSPI1_IO2
LVCMOS18
C4
DQ2_W_B
U183
BE18
QSPI1_IO3
LVCMOS18
D4
DQ3_HOLD_B
U183
AP20
QSPI1_CS_B
LVCMOS18
C2
S_B
U183
AB16
FPGA_CCLK
B2
C
U183
Notes:
1. Bank 0 V
CCO
= 1.8V; Bank 0 I/O standards are not specified.