Xilinx VC709, Руководство пользователя

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VC709 Evaluation Board www.xilinx.com 43
UG887 (v1.2.1) March 11, 2014
Feature Descriptions
Table 1-16 shows the USB connections between the FPGA and the UART.
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP
drivers.
I
2
C Bus
[ Figure 1-2 , callout 14 , 15 ]
The VC709 board implements a single I
2
C port on the FPGA (IIC_SDA_MAIN, pin AU32;
IIC_SDA_SCL, pin AT35), which is routed through a TI Semiconductor PCA9548A 1-to-8
channel I
2
C bus switch (U52). The bus switch can operate at speeds up to 400 kHz.
The bus switch I
2
C address is
0x74
(
0b01110100
) and must be addressed and configured
to select the desired downstream device.
The four SFP+ connectors SFP1 (P3), SFP2 (P2), SFP3 (P4), and SFP4 (P5) are addressed
through a secondary PCA9546A 1-to-4 channel I
2
C bus switch (U14). The VC709 board I
2
C
bus topology is shown in Figure 1-17 .
Table 1-15: USB Connector J17 Pin Assignments and Signal Definitions
USB Connector (J17)
Net Name Description
CP2103GM (U44)
Pin Name Pin Name
1 VBUS USB_UART_VBUS +5V VBUS powered
7 REGIN
8 VBUS
2 D_N USB_D_N Bidirectional differential serial data (N-side) 4 D –
3 D_P USB_D_P Bidirectional differential serial data (P-side) 3 D +
4 GND USB_UART_GND Signal ground
2 GND1
29 CNR_GND
Table 1-16: FPGA to UART Connections
FPGA
(U1)
Schematic
Net Name
CP2103GM
UART (U44)
Pin Function Direction IO Standard Pin Function Direction
AR34 RTS Output LVCMOS18 USB_UART_CTS 22 CTS Input
AT32 CTS Input LVCMOS18 USB_UART_RTS 23 RTS Output
AU36 TX Output LVCMOS18 USB_UART_RX 24 RXD Input
AU33 RX Input LVCMOS18 USB_UART_TX 25 TXD Output