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Copyright © 2015 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are property of their respective owners. 
 
Avnet Electronics Marketing 

19 of 28 

Rev D        24 Apr 2015 

 
 

2.5

 

User I/O and Expansion Connectors 

2.5.1

 

Peripheral Module (PMOD) 

Two 12-pin (2 x 6 female) Peripheral Module (PMOD) headers (J4, J5) are interfaced to the FPGA, with each 
header providing 3.3 V power, ground, and eight I/O’s.  These headers may be utilized as general-purpose I/Os 
or may be used to interface to PMODs. J4 and J5 are placed in close proximity (0.9”-centers) on the PCB in 
order to support dual PMODs.   Table 10 and Table 11 provide the connector and FPGA pinout.  For Digilent 
PMODs see: 

http://www.digilentinc.com/pmods  

Table 10 – Peripheral Module Connections – J4 

FPGA 

pin # 

I/O Signal 

Connector

Pin # 

Connector

Pin # 

I/O Signal 

FPGA 

pin # 

H12 FPGA_PMOD2_P1 

1 

7 

FPGA_PMOD2_P7  K12 

G13 FPGA_PMOD2_P2 

2 

8 

FPGA_PMOD2_P8  K13 

E16 FPGA_PMOD2_P3 

3 

9 

FPGA_PMOD2_P9  F17 

E18 FPGA_PMOD2_P4 

4 

10 

FPGA_PMOD2_P10 F18 

- 

GND

 

5 11 

GND

 

- 

- 

+3.3V_LS1 

6 12 

+3.3V_LS1 

- 

Table 11 – Peripheral Module Connections – J5 

FPGA 

pin # 

I/O Signal 

Connector

Pin # 

Connector

Pin # 

I/O Signal 

FPGA 

pin # 

F15 FPGA_PMOD1_P1 

1 

7 

FPGA_PMOD1_P7  F14 

F16 FPGA_PMOD1_P2 

2 

8 

FPGA_PMOD1_P8  G14 

C17 FPGA_PMOD1_P3 

3 

9 

FPGA_PMOD1_P9  D17 

C18 FPGA_PMOD1_P4 

4 

10 

FPGA_PMOD1_P10 D18 

- 

GND

 

5 11 

GND

 

- 

- 

+3.3V_LS1 

6 12 

+3.3V_LS1 

- 

 

 

Figure 8 – PMOD Connector Pinout 

 

 

 7   8   9 10 11 12

 1   2   3   4  5   6

 7   8   9 10 11 12

 1   2   3   4  5   6

Содержание Spartan-6 LX9

Страница 1: ...Xilinx Spartan 6 LX9 MicroBoard User Guide Revision D...

Страница 2: ...versal Serial Bus USB 2 0 Full Speed USB to JTAG bridge via Atmel AT90USB162 ATMEGA162U2 AVR Microcontroller and TE Connectivity USB A connector 16 2 4 2 USB UART 16 2 4 3 10 100 Ethernet PHY via Texa...

Страница 3: ...100 Ethernet Interface 17 Figure 8 PMOD Connector Pinout 19 Figure 9 TPS65708 Connections 21 Figure 10 Xilinx Ribbon Cable JTAG Connector 24 Tables Table 1 Ordering Information 7 Table 2 CDCE913 Clock...

Страница 4: ...ion The Spartan 6 FPGA LX9 MicroBoard provides a complete hardware environment for designers to accelerate their time to market The kit delivers a stable platform to develop and test designs targeted...

Страница 5: ...10 100 Ethernet port via Texas Instruments DP83848J PHY and TE Connectivity RJ45 connector with Integrated Magnetics User I O and Expansion Connectors o Two Digilent 12 pin 0 245mm pitch Peripheral M...

Страница 6: ...e and can be found on the Avnet Electronics Marketing Design Resource Center DRC web site www em avnet com s6microboard See the PDF document included with each reference design for a complete descript...

Страница 7: ...Ordering Information The following table lists the evaluation kit part numbers and available software options Table 1 Ordering Information Part Number Hardware AES S6MB LX9 G Xilinx Spartan 6 FPGA LX...

Страница 8: ...mponent of the Avnet Spartan 6 FPGA LX9 MicroBoard A 10 100 Ethernet port and two Full Speed USB interfaces provide means of off board communication On board memory consists of a 256 Mbit x 16 LPDDR m...

Страница 9: ...e clock management blocks SelectIO technology advanced system level power management modes auto detect configuration options and enhanced IP security with Device DNA protection These features provide...

Страница 10: ...t Electronics Marketing 10 of 28 Rev D 24 Apr 2015 Bank0 44 IOs 3 3V Bank2 44 IOs 3 3V VCCINT and Ground Bank1 56 IOs 3 3V Bank3 56 IOs 1 8V SPI Flash 6 I Os LPDDR MCB 41 I Os User DIP 4 I Os RZQ 1 I...

Страница 11: ...3 during factory configuration Table 2 CDCE913 Clocks Clock CDCE913 Pin Signal Name FPGA Pin 40 MHz U1 pin 11 Y1 USER_CLOCK V10 GCLK0 66 7 MHz U1 pin 9 Y2 CLOCK_Y2 K15 GCLK9 100 MHz U1 pin 8 Y3 CLOCK_...

Страница 12: ...d with both LPDDR mobile SDRAM memory 256 Mbit x 16 and 128 Mbit SPI Multi I O Flash to support various types of applications The SPI Flash may be used for FPGA configuration Figure 5 shows a high lev...

Страница 13: ...supports up to 400 Mb s 200 MHz double data rate performance The following figure shows a high level block diagram of the LPDDR Mobile SDRAM interface on the MicroBoard Figure 6 Spartan 6 FPGA LX9 LPD...

Страница 14: ...55000 Delay after AUTOREFRESH Command TRFC 75000 Delay after ACT before READ WRITE TRCD 15000 Delay after ACT before another row ACT TRRD 10000 Delay after PRECHARGE Command TRP 15000 Refresh Command...

Страница 15: ...8 FPGA_D1_MISO2 W VPP DQ2 U2 pin 3 DQ2 T14 NC FPGA_D2_MISO3 HOLD DQ3 U2 pin 7 DQ3 V14 NC FPGA_CCLK CLK U2 pin 6 C R15 U3 pin 11 FPGA_SPI CS SEL U2 pin 1 S_N V3 U3 pin 10 FPGA_PROG PROGRAM_B NC V2 U3 p...

Страница 16: ...tly to the SPI Flash is accomplished using the command line sfutil exe Both configurations make use of custom Digilent firmware loaded into the AT90USB162 ATMEGA162U2 device during manufacture The SPI...

Страница 17: ...nectivity RJ45 connector includes integrated magnetics and LEDs A MAC must be placed inside the FPGA such as the AXI Ethernet Lite AXI Tri Mode Ethernet Media Access Controller TEMAC XPS Ethernet Lite...

Страница 18: ...PGA_ETH_CRS N17 FPGA_ETH_RESET T18 Please note that the PHY Address pins are not strapped on the board The Avnet XBD for this board places pull ups on the AD 4 1 pins The AD 0 pin is shared with COL w...

Страница 19: ...0 and Table 11 provide the connector and FPGA pinout For Digilent PMODs see http www digilentinc com pmods Table 10 Peripheral Module Connections J4 FPGA pin I O Signal Connector Pin Connector Pin I O...

Страница 20: ...to a logic 1 and are off when the pin is either low 0 or not driven Table 12 LED Pin Assignments Net Name Reference FPGA Pin FPGA_GPIO_LED1 D2 P4 FPGA_GPIO_LED2 D3 L6 FPGA_GPIO_LED3 D9 F5 FPGA_GPIO_LE...

Страница 21: ...08 The input voltage is the 1 8V generated by DCDC2 The DCDC2 regulator generates 1 8V This voltage powers the Mobile DDR FPGA Vcco and the LDO2 source Estimated max current is 210mA plus the 160mA th...

Страница 22: ...aller package is acceptable and in fact provides better characteristics than the 0805 package 100uF 6 3V 1206 package capacitor is used for the bulk capacitor bin Again a smaller package is used Pleas...

Страница 23: ...irements such as Power rail assignment o Spartan 6 Vccint 1 2 V o Spartan 6 Vccaux 3 3 V o Spartan 6 Vcco_0 _1 _2 3 3 V o Spartan 6 Vcco_3 1 8 V o LPDDR VDD VDDQ 1 8 V o TPS65708 VCC VIN1 VIN2 7 5 V T...

Страница 24: ...OG pin and pulled up Pushing the button connects PROG to ground Upon releasing the button a re configuration is initiated This line can also be pulled low by the AT90USB162 ATMEGA162U2 In this case it...

Страница 25: ...roBoard factory test is programmed into the Micron SPI Flash as part of the functional test when the boards are built The results of this test are described in the Xilinx Spartan 6 LX9 MicroBoard Gett...

Страница 26: ...Full Speed USB to JTAG bridge via Atmel ATMEGA162U2 Micron www micron com solutions partner ecosystem xilinx Multi I O SPI Flash LPDDR Memory Texas Instruments www ti com xilinxfpga Clock PLL Power Ma...

Страница 27: ...et Spartan 6 FPGA LX9 MicroBoard forum http community em avnet com t5 Spartan 6 LX9 MicroBoard bd p Spartan 6LX9MicroBoard For Xilinx technical support you may contact Xilinx Online Technical Support...

Страница 28: ...to USER_RESET to reflect actual polarity Updated TBD references Changed reference to Factory Test availability on DRC to Avnet Silica FAE Removed version reference for DVD WebPACK C 11 6 2011 Added th...

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