Platform Cable USB II
DS593 (v1.2.1) March 17, 2011
22
Pseudo Ground Signal
The pseudo ground (PGND) pin on target interface connector is routed to a ultra-high-speed buffer with an open-drain output
(
). A pull-up resistor is required on target systems that utilize this signal. The buffer can tolerate a pull-up voltage
as high as 6.0V.
HALT_INIT_WP Signal in iMPACT
Platform Cable USB II provides a second multi-use signal on its target interface connector called HALT_INIT_WP (this signal
is referred to as HALT when the cable is in JTAG mode). The HALT_INIT_WP pin is connected to a three-state CMOS driver
(see
Bidirectional Signal Pins, page 19
).
The behavior of HALT_INIT_WP is determined by the host application connected to the cable. iMPACT provides the option
of enabling the HALT pin during JTAG operations (
). This option is accessed by clicking on the Xilinx FPGA in the
iMPACT GUI and selecting
Edit
→
Set Programming Properties…
to open the Device Programming Properties dialog box.
Check “Assert Cable INIT during programming” to enable the HALT signal.
When enabled in iMPACT, HALT is active-Low while the cable is performing JTAG operations on any Xilinx FPGA and high-
Z when the cable is idle. HALT is active-High while JTAG operations are being performed on other devices. The HALT signal
remains high-Z when not enabled (iMPACT default) or when the cable is in Slave Serial or SPI modes.
Note:
HALT signal control is available in iMPACT 9.2i and later. HALT remains high-Z in earlier versions of iMPACT and in Xilinx design
tools where the HALT signal is not supported.
X-Ref Target - Figure 23
Figure 23:
PGND Signal
FPGA
NC7WZ07
PGND_CNTL
PGND
2-mm Connector
DS593_23_021508
Y
A
Input
A
Output
Y
H
L
L
Z
