Modifying Xilinx ML605 for Direct JTAG Access
3
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Description of the Modification
This section describes the steps to make the JTAG signals accessible for debugging. The description
assumes a board orientation with the display towards the user (“South”) and the connectors for the adaptor
cards (HMC LCP, HMC HPC) facing away from the user (“North”).
1.
The TDO signal (last device) is retrieved by soldering a cable to the left pin of the resistor R296.
The cable is later connected to the free pin on the “PPC to HW-FMC-105-DEBUG” adaptor.
The resistor R296 is located at the front side of the board, close to the south-west corner of the FMC
LPC connector.
2.
Disable the driver U88 (SN74LV541APWR) so that the debugger can drive the signals. U88 is
located at the back side in the north-west quadrant of the board.
The driver is disabled by bowing up pin 19 (OE2_N) and connecting it to pin 20 (creating a connection
to VCC). Also connect pins 16 & 17 and pins 13 & 14 so that the debugger can drive the TMS and
TCK nets for the SysACE and Virtex6.
3.
Attach the HW-FMC-105-DEBUG daughter board to the FMC-LPC connector J63.
Jumper J17 to “EXC HPC” and
J18 to “INC LPC”
settings.
Attach the “JTAG to Xilinx ML605” adaptor to J5 on the daughter board.
Connect the cable from R296 to the free “needle” on the “JTAG to Xilinx ML605” adaptor.
Target top view, cable for TDO attached to R296 (left), JTAG to Xilinx ML605 adaptor (right).
In the PDF version, you can zoom into the photo for details.
