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ML52

User Guide

www.xilinx.com

UG225 (v2.1) August 4, 2010

Detailed Description

21. RS-232 Port Pins

The RS-232 port pin connections to the DUT are as shown in

Table 18

. The pins are set up

in DTE mode as shown in

Figure 4

22. Xilinx Generic Interface (XGI)

The XGI is an expansion interface for plug-in modules (for example, the SuperClock
module) and provides the user access to the I/O pins listed in the tables below.

Table 19

(spanning multiple pages) shows the schematic pinout of the XGI interface

converted to an alphanumeric column and row format.

Table 18:

RS-232 Port Pins

Pin Name

Direction

Port Name

ML521

ML523

ML525

TXD

OUT

T1IN

G14

L16

P17

RTS

OUT

T2IN

H13

L15

P18

RXD

R1OUT

G16

L20

P25

CTS

R2OUT

G15

L21

N25

X-Ref Target - Figure 4

Figure 4:

RS-232 Pins in DTE Mode

UG225_04_112807

RS232

DB9

Virtex-5

T1IN

TXD

RTS

RXD

CTS

Pin 3

Pin 7

Pin 2

Pin 8

T2IN

R1OUT

R2OUT

Table 19:

Top View of PCB

Column

Row

J113

J135

J136

J118

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Elcodis.com

electronic components distributor

Содержание ML52 Series

Страница 1: ...R ML52x User Guide Virtex 5 FPGA RocketIO Characterization Platform UG225 v2 1 August 4 2010 0402527 03 Downloaded from Elcodis com electronic components distributor...

Страница 2: ...property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 03 02 07 1 0 Initial Xilinx release 08 06 07 1 1 Removed UG...

Страница 3: ...LED 15 6 INIT LED 15 7 System ACE Controller 16 8 Reset Switch Active Low 16 9 Configuration Address DIP Switch 16 10 JTAG Isolation Jumpers 16 11 System ACE MPU Port 17 12 Oscillator Sockets 18 13 Si...

Страница 4: ...4 www xilinx com ML52x User Guide UG225 v2 1 August 4 2010 R Downloaded from Elcodis com electronic components distributor...

Страница 5: ...x 5 FPGA User Guide Chapters in this guide cover the following topics Clocking Resources Clock Management Technology CMT Phase Locked Loops PLLs Block RAM Configurable Logic Blocks CLBs SelectIO Resou...

Страница 6: ...rough the SelectMAP and JTAG interfaces Virtex 5 FPGA System Monitor User Guide The System Monitor functionality available in all the Virtex 5 devices is outlined in this guide Virtex 5 FPGA Packaging...

Страница 7: ...rmation Emphasis in text The address F is asserted after clock event 2 Underlined Text Indicates a link to a web page http www xilinx com virtex5 Convention Meaning or Use Example Blue text Cross refe...

Страница 8: ...8 www xilinx com ML52x User Guide UG225 v2 1 August 4 2010 Preface About This Guide R Downloaded from Elcodis com electronic components distributor...

Страница 9: ...52x The information includes Current version of this user guide in PDF format Example design files for demonstration of Virtex 5 FPGA features and technology Demonstration hardware and software config...

Страница 10: ...g the board The platforms and their corresponding packages are shown in Table 1 Features Virtex 5 FPGA referred to as the device under test or DUT in this user guide Onboard power supplies for all nec...

Страница 11: ...LED LEDs GP SWs PB SW 1 PB SW 2 DDR2 UG225_01_032608 Virtex 5 FPGA DUT GTP GTX Transceivers Active High Active High DIFF SMA DIFF SMA CC OSC SMA OSC Socket GTP GTX Transceiver Clock SMA DIFF SMA 8 Tra...

Страница 12: ...s user guide Each feature is detailed in the numbered sections that follow Note The image might not reflect the current revision of the board X Ref Target Figure 2 Figure 2 Detailed Description of Vir...

Страница 13: ...lation Main Board Regulation The ML52x platform has onboard regulation for the DUT main power supplies listed in Table 2 These regulators also have a corresponding input voltage jack to supply each vo...

Страница 14: ...T GND N A N A J102 J103 N A Ground connection for all circuits Table 2 Onboard Regulation Voltage Current Jacks and Jumpers Cont d Power Supply Name Max Current Rating Typical Voltage Jack Connector E...

Страница 15: ...am Switch Active Low The active Low program switch when pressed grounds the program pin on of the FPGA 5 DONE LED The DONE LED indicates the status of the DONE pin of the FPGA The LED lights when DONE...

Страница 16: ...an be read The open O position indicates a logic 0 and the closed C position indicates a logic 1 as shown in Table 4 10 JTAG Isolation Jumpers The 2 pin headers shown in Table 5 provide the ability fo...

Страница 17: ...see System ACE CompactFlash Solution Ref 1 Table 6 System ACE Port Connections Pin Name ML521 ML523 ML525 MPA00 K7 E8 N8 MPA01 K6 E9 N9 MPA02 U5 K9 G8 MPA03 R5 C13 U9 MPA04 N6 E11 V11 MPA05 P6 F11 U11...

Страница 18: ...llator Sockets Connections Ref Des Enable Disable Jumper Power Select Jumper Pin Name ML521 ML523 ML525 X2 J114 J115 CLK_IN_B AB19 AG21 AP27 X3 J117 J116 CLK_IN_A D18 1 J19 1 K29 Notes 1 For ML521 and...

Страница 19: ...ED ML521 ML523 ML525 DS16 LED8 AE6 AJ25 AP37 DS17 LED7 AF5 AH25 AP36 DS18 LED6 AE8 AH27 AH35 DS19 LED5 AE7 AJ26 AG36 DS20 LED4 AB6 AK28 AH34 DS21 LED3 AB7 AK27 AG34 DS22 LED2 AF12 AA25 AB33 DS23 LED1...

Страница 20: ...rpose that the user sees fit Table 12 User DIP Switches Top Column Ref Des Net Name ML521 ML523 ML525 S1 SW8 W9 AB27 AC33 SW7 W8 AC27 AD32 SW6 AE11 AD24 AL34 SW5 AD11 AE24 AK34 SW4 V8 AD26 AL36 SW3 V9...

Страница 21: ...tial IOBs DIFF_SSTL18_II and DIFF_SSTL18_II_DCI for clock and data strobe signals Table 15 shows the DDR2 connections to the DUT For more information on the DDR2 memory devices refer to the Micron DDR...

Страница 22: ...D25 T25 W37 D15 D26 U25 W36 D16 B14 G30 G38 D17 A15 J29 F40 D18 A14 H29 F39 D19 C16 E31 E40 D20 B15 F31 E39 D21 B16 L29 R39 D22 A17 G31 P37 D23 B17 H30 R37 D24 G24 M26 P36 D25 F24 M25 N36 D26 E23 J27...

Страница 23: ...1 AL39 D47 AF14 AF30 AP38 D48 N23 N25 W32 D49 N24 P25 Y33 D50 M22 T24 AA32 D51 N22 R24 Y32 D52 G26 L26 M36 D53 F25 L25 N35 D54 G25 J25 M37 D55 H26 J24 L37 D56 AF24 W27 AD37 D57 AF25 Y27 AD36 D58 AF23...

Страница 24: ...C21 N30 K39 DQS2 C19 K31 K38 DQS2 D19 L31 J38 DQS3 J21 G27 U34 DQS3 K21 H27 T35 DQS4 AF22 Y28 AN40 DQS4 AE21 Y29 AP40 DQS5 AC21 AA29 AT39 DQS5 AD21 AA30 AR39 DQS6 L23 E28 R35 DQS6 L22 F28 T36 DQS7 AF2...

Страница 25: ...Y3 AD3 J47 REFCLKP_114 T4 Y4 AD4 J15 REFCLKN_116 D3 H3 M3 J13 REFCLKP_116 D4 H4 M4 J28 REFCLKN_118 AB3 AF3 AK3 J37 REFCLKP_118 AB4 AF4 AK4 J68 REFCLKN_120 D4 F3 J77 REFCLKP_120 E4 F4 J88 REFCLKN_122...

Страница 26: ...52 RXP1_112 M1 T1 Y1 J49 TXN1_112 M2 T2 Y2 J50 TXP1_112 N2 U2 AA2 J46 RXN0_114 T1 Y1 AD1 J45 RXP0_114 R1 W1 AC1 J43 TXN0_114 R2 W2 AC2 J44 TXP0_114 P2 V2 AB2 J41 RXN1_114 U1 AA1 AE1 J42 RXP1_114 V1 AB...

Страница 27: ...122 AK2 AP2 J91 RXN1_122 AP2 AU1 J92 RXP1_122 AP3 AV1 J89 TXN1_122 AN3 AV2 J90 TXP1_122 AN4 AW2 J66 RXN0_124 A8 A4 J65 RXP0_124 A9 A5 J63 TXN0_124 B9 B5 J64 TXP0_124 B10 B6 J61 RXN1_124 A7 A3 J62 RXP1...

Страница 28: ...A16 J145 RXP0_132 A17 J144 TXN0_132 B17 J157 TXP0_132 B18 J142 RXN1_132 A15 J143 RXP1_132 A14 J21 TXN1_132 B14 J141 TXP1_132 B13 J178 RXN0_134 BB15 J165 RXP0_134 BB14 J164 TXN0_134 BA14 J177 TXP0_134...

Страница 29: ...ges shows the schematic pinout of the XGI interface converted to an alphanumeric column and row format Table 18 RS 232 Port Pins Pin Name Direction Port Name ML521 ML523 ML525 TXD OUT T1IN G14 L16 P17...

Страница 30: ...14 27 28 14 14 27 28 15 29 30 15 15 29 30 16 31 32 16 16 31 32 17 33 34 17 17 33 34 18 35 36 18 18 35 36 19 37 38 19 19 37 38 20 39 40 20 20 39 40 21 41 42 21 21 41 42 22 43 44 22 22 43 44 23 45 46 23...

Страница 31: ...I_DIFF_6P E6 G33 N40 D13 VCCO F27 GND E28 XGI_DIFF_6N D6 F34 P40 D14 VCCO F29 GND E30 XGI_DIFF_7P C9 J32 W40 D15 VCCO F31 GND E32 XGI_DIFF_7N D8 H33 Y40 D16 VCCO F33 GND E34 XGI_DIFF_8P C7 H34 AA40 D1...

Страница 32: ...CFG TMS CFG TMS C12 CFG TCK CFG TCK CFG TCK CFG TCK C13 EX TDO EX TDO EX TDO EX TDO C14 FPGA TDO FPGA TDO FPGA TDO FPGA TDO C15 XGI_SE_32 E5 T34 Y42 C16 XGI_SE_33 D5 U33 W42 C17 XGI_SE_34 D11 U31 AA41...

Страница 33: ...AD42 B25 GND A26 XGI_SE_12 V21 AN32 AU42 B27 GND A28 XGI_SE_13 W21 AP32 AV41 B29 GND A30 XGI_SE_14 U21 AN34 AT41 B31 GND A32 XGI_SE_15 V22 AN33 AU41 B33 GND A34 XGI_SE_16 T22 AM33 AR42 B35 GND A36 XGI...

Страница 34: ...d 1 J24 RSVD J126 DDR VOLTAGE SELECT 2 3 J114 X2 OSCILLATOR ENABLE Installed 1 1 2 J115 X2 OSCILLATOR VOLTAGE J116 X3 OSCILLATOR VOLTAGE J117 X3 OSCILLATOR ENABLE J128 JTAG TDI J129 JTAG TDO J131 JTAG...

Страница 35: ...ilinx Generic Interface XGI SuperClock Module User Guide 3 UG190 Virtex 5 FPGA User Guide 4 UG196 Virtex 5 FPGA RocketIO GTP Transceiver User Guide 5 UG198 Virtex 5 FPGA RocketIO GTX Transceiver User...

Страница 36: ...36 www xilinx com ML52x User Guide UG225 v2 1 August 4 2010 References R Downloaded from Elcodis com electronic components distributor...

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