Xilinx ML501, Руководство пользователя

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ML501 Reference Design www.xilinx.com 7
UG227 (v1.0) June 18, 2007
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ML501 Reference Design
Introduction
The Virtex-5 family of FPGAs [Ref 1] offers designers multiple platforms with an
optimized balance of high-performance logic, serial connectivity, signal processing, and
embedded processing resources. All members of the Virtex-5 family are built using the
second generation Advanced Silicon Modular Block (ASMBL™) technology and a state-of-
the-art 65 nm copper process to produce the industry's highest performance FPGAs.
Along with capabilities offered directly through an integrated IP block implemented in
silicon, the Xilinx
LogiCORE IP catalog and the embedded processing IP catalog are
available to system level designers. Constructing embedded processing systems is
significantly simplified by the Base System Builder (BSB) wizard provided as part of the
Embedded Development Kit (EDK).
Users can obtain a quick understanding of the features offered by the ML501 boards by
running the demonstration content provided on the CompactFlash (CF) card included
with each board.
ML501 Getting Started Tutorial [Ref 2] shows how to configure the ML501
from the ACE files pre-loaded on the CF card and describes what to observe for expected
output.