112
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 3:
MicroBlaze Signal Interface Description
Local Memory Bus (LMB) Interface Description
The LMB is a synchronous bus used primarily to access on-chip block RAM. It uses a minimum
number of control signals and a simple protocol to ensure that local block RAM are accessed in a
single clock cycle. LMB signals and definitions are shown in the following table. All LMB signals
are active high.
LMB Signal Interface
Addr[0:31]
The address bus is an output from the core and indicates the memory address that is being accessed
by the current transfer. It is valid only when AS is high. In multicycle accesses (accesses requiring
more than one clock cycle to complete),
Addr[0:31]
is valid only in the first clock cycle of the
transfer.
Byte_Enable[0:3]
The byte enable signals are outputs from the core and indicate which byte lanes of the data bus
contain valid data.
Byte_Enable[0:3]
is valid only when AS is high. In multicycle accesses
(accesses requiring more than one clock cycle to complete),
Byte_Enable[0:3]
is valid only in
the first clock cycle of the transfer. Valid values for
Byte_Enable[0:3]
are shown in the
following table:
Table 3-4:
LMB Bus Signals
Signal
Data Interface
Instruction
Interface
Type
Description
Addr[0:31]
Data_Addr[0:31]
Instr_Addr[0:31]
O
Address bus
Byte_Enable[0:3]
Byte_Enable[0:3]
not used
O
Byte enables
Data_Write[0:31]
Data_Write[0:31]
not used
O
Write data bus
AS
D_AS
I_AS
O
Address strobe
Read_Strobe
Read_Strobe
IFetch
O
Read in progress
Write_Strobe
Write_Strobe
not used
O
Write in progress
Data_Read[0:31]
Data_Read[0:31]
Instr[0:31]
I
Read data bus
Ready
DReady
IReady
I
Ready for next
transfer
Wait
1
1. Added in LMB for MicroBlaze v8.00
DWait
IWait
I
Wait until accepted
transfer is ready
CE
DCE
ICE
I
Correctable error
UE
DUE
IUE
I
Uncorrectable error
Clk
Clk
Clk
I
Bus clock
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