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Ethernet AVB Endpoint User Guide

UG492 September 21, 2010

Preface:

About This Guide

List of Abbreviations

The following table describes acronyms used in this manual.

Acronym

Spelled Out

Audio Video

AVB

Audio Video Bridging

BMCA

Best Master Clock Algorithm

CRC

Cyclic Redundancy Check

Destination Address

DMA

Direct Memory Access

DSP

Digital Signal Processor

EDK Embedded

Development

Kit

EMAC

Ethernet MAC

FCS

Frame Check Sequence

FIFO

First In First Out

FPGA

Field Programmable Gate Array.

Gbps

Gigabits per second

GMII

Gigabit Media Independent Interface

GUI

Graphical User Interface

HDL

Hardware Description Language

IES

Incisive Unified Simulator

I/F

Interface

Input/Output

Intellectual Property

ISE®

Integrated Software Environment

KHz

Kilo Hertz

LLDP

Link Layer Discovery Protocol

MAC

Media Access Controller

Mbps

Megabits per second

MDIO

Management Data Input/Output

MHS

Microprocessor Hardware Description: a proprietary file format,
using the .mhs file extension, for a XPS project

MHz

Mega Hertz

milliseconds

MPMC

Multi-Port Memory Controller

nanoseconds

Содержание LogiCORE Endpoint v2.4

Страница 1: ...LogiCORETM IP Ethernet AVB Endpoint v2 4 User Guide UG492 September 21 2010...

Страница 2: ...tocopying recording or otherwise without the prior written consent of Xilinx 2008 2010 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks o...

Страница 3: ...24 Additional Core Resources 24 Technical Support 24 Feedback 24 Ethernet AVB Endpoint Core 24 Document 25 Chapter 2 Licensing the Core Before you Begin 27 License Options 27 Simulation Only 27 Full S...

Страница 4: ...recise Timing Protocol Blocks 44 Software Drivers 46 Tri Mode Ethernet MACs 46 Core Interfaces 47 Clocks and Reset 47 Legacy Traffic Interface 48 AV Traffic Interface 49 Tri Mode Ethernet MAC Client I...

Страница 5: ...90 Ethernet AVB Endpoint Address Space 92 Tri Mode Ethernet MAC Address Space 100 Chapter 11 Constraining the Core Required Constraints 103 Device Package and Speedgrade Selection 103 I O Location Co...

Страница 6: ...Next 142 Chapter 15 Detailed Example Design Standard Format Directory and File Contents 144 project directory 144 project directory component name 145 component name doc 145 component name example des...

Страница 7: ...a 161 pcores eth_avb_endpoint_v2_04_a data 161 pcores eth_avb_endpoint_v2_04_a hdl vhdl 162 pcores eth_avb_endpoint_v2_04_a netlist 162 MyProcessorIPLib drivers avb_v2_04_a 162 drivers avb_v2_04_a dat...

Страница 8: ...8 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010...

Страница 9: ...e 6 2 Legacy Frame Transmission with Underrun 59 Figure 6 3 Normal Frame Transmission across the AV Traffic Interface 60 Figure 6 4 Credit based Shaper Operation 62 Chapter 7 Ethernet AVB Endpoint Rec...

Страница 10: ...ection to the Virtex 5 FPGA Embedded Tri Mode Ethernet MAC and Ethernet Statistic Core 118 Figure 12 5 Connection of the Ethernet AVB Endpoint Core into an Embedded Processor Sub system 120 Figure 12...

Страница 11: ...September 21 2010 Chapter 16 Detailed Example Design EDK format Appendix A RTC Time Stamp Accuracy Figure A 1 RTC Periodic Error 168 Figure A 2 RTC Sampling Logic 169 Figure A 3 Sampling Position Unc...

Страница 12: ...12 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010...

Страница 13: ...ble 5 8 Tri Mode Ethernet MAC Host Interface Configuration Status 51 Table 5 9 PLB Signals 53 Table 5 10 Interrupt Signals 55 Table 5 11 PTP Signals 56 Chapter 6 Ethernet AVB Endpoint Transmission Cha...

Страница 14: ...n Registers 98 Table 10 17 Tri Mode Ethernet MAC and Ethernet Statistics Configuration Registers 100 Chapter 11 Constraining the Core Chapter 12 System Integration Chapter 13 Software Drivers Chapter...

Страница 15: ...Endpoint User Guide www xilinx com 15 UG492 September 21 2010 Table 16 7 Driver Data Directory 163 Table 16 8 Driver Example Directory 163 Table 16 9 Driver Source Directory 164 Appendix A RTC Time St...

Страница 16: ...16 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010...

Страница 17: ...the core using the CORE Generator software Chapter 5 Core Architecture describes the major functional blocks of the Ethernet AVB Endpoint core Chapter 6 Ethernet AVB Endpoint Transmission describes d...

Страница 18: ...me stamps essential to the Precise Timing Protocol across the network link and provides some of the ways inaccuracies are introduced Conventions This document uses the following conventions An example...

Страница 19: ...itive material that has been omitted allow block block_name loc1 loc2 locn Notations The prefix 0x or the suffix h indicate hexadecimal notation A read of address 0x00112975 returned 45524943h An _n m...

Страница 20: ...uence FIFO First In First Out FPGA Field Programmable Gate Array Gbps Gigabits per second GMII Gigabit Media Independent Interface GUI Graphical User Interface HDL Hardware Description Language IES In...

Страница 21: ...Stream Reservation Protocol TEMAC Tri Mode Ethernet MAC TCP IP Transmission Control Protocol Internet Protocol TOE TCP IP Offload Engine Tx Transmitter UCF User Constraints File us microseconds VHDL V...

Страница 22: ...22 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010 Preface About This Guide...

Страница 23: ...nd VHDL formats System Requirements Windows Windows XP Professional 32 bit 64 bit Windows Vista Business 32 bit 64 bit Linux Red Hat Enterprise Linux WS v4 0 32 bit 64 bit Red Hat Enterprise Desktop v...

Страница 24: ...Ethernet AVB Endpoint core see the following documents available from the product page Ethernet AVB Endpoint Data Sheet Ethernet AVB Endpoint User Guide From the document directory after generating th...

Страница 25: ...ck Document For comments or suggestions about this document submit a WebCase from www xilinx com support clearexpress websupport htm Be sure to include the following information Document title Documen...

Страница 26: ...26 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010 Chapter 1 Introduction...

Страница 27: ...e a license option Simulation Only The Simulation Only Evaluation license key is provided with the ISE CORE Generator tool This key lets you assess core functionality with either the example design pr...

Страница 28: ...ow the instructions to install the required Xilinx ISE software and IP Service Packs Obtaining a Full License Key To obtain a Full license key please follow these instructions 1 Purchase the license t...

Страница 29: ...potential audio video talkers for example a Cable or Satellite Content Provider or home MP3 player and a number of potential listeners for example TV sets which may exist in several rooms In addition...

Страница 30: ...e clock master by automatic resolution using a Best Master Clock Algorithm BMCA All other devices resolve to be slaves Using the P802 1AS PTP all slave devices will regularly update their own RTC to m...

Страница 31: ...V traffic port In this case the Ethernet AVB Endpoint will not prioritize SR Class A Ethernet frames over SR Class B Ethernet frames instead it will apply the credit based shaper algorithm to all of t...

Страница 32: ...P802 1Qat specification because this is a pure software task This software is not provided by the Ethernet AVB Endpoint core Typical Implementation Figure 3 2 illustrates a typical implementation for...

Страница 33: ...bandwidth restrictions 2 The legacy traffic interface is maintained for best effort ethernet data Ethernet as we know it today for example the PC surfing the internet in Figure 3 1 Wherever possible p...

Страница 34: ...34 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010 Chapter 3 Overview of Ethernet Audio Video Bridging...

Страница 35: ...cal User Interface GUI for defining parameters and options For help starting and using the CORE Generator software see the documentation supplied with the ISE software including the CORE Generator Use...

Страница 36: ...he core is designed to interface to the LogiCORE IP Tri Mode Ethernet MAC or the LogiCORE IP Embedded Tri Mode Ethernet MAC wrappers available in selected Virtex families See Chapter 12 System Integra...

Страница 37: ...net AVB Endpoint core is a PLB slave On the connected PLB there may be several PLB Masters Each slave must uniquely acknowledge individual masters using unique PLB signals during transactions For this...

Страница 38: ...ntation Subdirectories containing an HDL example design Scripts to run the core through the back end tools and to simulate the core using Mentor Graphics ModelSim v6 5c Cadence Incisive Enterprise Sim...

Страница 39: ...luding previous versions of this core and all other Ethernet LogiCORE IP solutions When generated in this format the core is designed to interface to the LogiCORE IP Tri Mode Ethernet MAC or the LogiC...

Страница 40: ...s the MAC to be fully configured via the PLB Interface of the Ethernet AVB Endpoint core The core provides two independent full duplex interfaces for customer logic the AV Traffic Interface and the Le...

Страница 41: ...is connected directly to the xps_ll_temac this allows the xps_ll_temac core to source and sink legacy frame data such as TCP IP protocol traffic The full duplex AV Traffic Interface remains for connec...

Страница 42: ...ee Chapter 10 Configuration and Status for more information AV Traffic Interface The AV traffic interface provides a dedicated full duplex port for the high priority AV data See Chapter 6 Ethernet AVB...

Страница 43: ...ork can be of three types Precise Timing Protocol PTP Packets Routed to the dedicated hardware Rx PTP Packet Buffers which can be accessed by the Software Drivers PTP packets are identified by searchi...

Страница 44: ...current nanosecond value of the local RTC is taken This timestamp value is written into a dedicated field within the Tx PTP Packet Buffer where it is accessible along side the content of the PTP fram...

Страница 45: ...8576 1 220 fraction of one nanosecond For this reason the RTC increment rate can be adjusted to a very fine degree of accuracy This provides the following features The RTC can be incremented from any...

Страница 46: ...master This is achieved in part by receiving the PTP frames transmitted across the network by the clock master and containing the masters sampled RTC value The PTP mechanism will also track the total...

Страница 47: ..._clk_en Input A clock enable signal this must be used as a qualifier for tx_clk rx_clk Input The MAC receiver clock provided by the Tri Mode Ethernet MAC rx_clk_en Input A clock enable signal this mus...

Страница 48: ...client All signals are synchronous to the MAC receiver clock rx_clk which must be qualified by the corresponding clock enable rx_clk_en see Clocks and Resets Table 5 2 Legacy Traffic Signals Transmit...

Страница 49: ...d for the PTP or AV traffic channel legacy_rx_filter_match 7 0 Output This output is only present when the MAC Header Filters are present when the core is generated in Standard CORE Generator Format W...

Страница 50: ...net MAC signals and are synchronous to tx_clk Table 5 5 AV Traffic Signals Receiver Path Signal Direction Description av_rx_data 7 0 Output AV frame data received is supplied on this port av_rx_valid...

Страница 51: ...d on this port rx_data_valid Input Control signal for the rx_data 7 0 port rx_frame_good Input Asserted at the end of frame reception to indicate that the frame should be processed by the Ethernet AVB...

Страница 52: ...different peripheral bus widths The general philosophy of the Ethernet AVB Endpoint core has been to implement a PLB interface which is as simple as possible The following features are provided 32 bit...

Страница 53: ...Input Unused PLB secondary to primary read request indicator PLB_wrPrim Input Unused PLB secondary to primary write request indicator PLB_masterID 0 log2 NUM_MASTERS Input PLB current master identifi...

Страница 54: ...rite transfer complete indicator Sl_WrBTerm Output Slave terminate write burst transfer Sl_rdBus 0 31 Output Slave read data bus Sl_rdWdAddr 0 3 Output Slave read word address Sl_rdDAck Output Slave r...

Страница 55: ...s recommended that these interrupts are routed to the input of an EDK Interrupt Controller module as part of the embedded processor subsystem Table 5 10 Interrupt Signals Signal Direction Description...

Страница 56: ...ield used in the 1722 presentation time stamp logic Table 5 11 PTP Signals Signal Direction Description rtc_nanosec_field 31 0 Output This is the synchronized nanoseconds field from the RTC rtc_sec_fi...

Страница 57: ...the core Tx Legacy Traffic I F The signals forming the Tx Legacy Traffic I F are defined in Table 5 2 All signals are synchronous to the Tri Mode Ethernet MAC transmitter clock tx_clk which must alway...

Страница 58: ...erts a logic 1 onto legacy_tx_data_valid After the Ethernet AVB Endpoint core reads the first byte of data it asserts the legacy_tx_ack signal On the next and subsequent rising clock edges the client...

Страница 59: ...are defined in Table 5 4 All signals are synchronous to the Tri Mode Ethernet MAC transmitter clock tx_clk which must always be qualified by the corresponding clock enable tx_clk_en see Table 5 1 See...

Страница 60: ...t frame and the frame transmission cycle of Figure 6 3 repeats However if no further AV traffic frames are queued the av_tx_done signal should be set to logic 1 immediately following the end of frame...

Страница 61: ...traffic having a higher priority than the legacy traffic there is always remaining bandwidth available to schedule legacy traffic The relevant configuration registers for programming the bandwidth per...

Страница 62: ...raffic is queued any positive credit will be lost and the credit is reset to 0 When AV traffic is queued and until the time at which the Tx Arbiter is able to schedule it while waiting for an in progr...

Страница 63: ...configuration register settings are described in general and then from the point of view of a single example which describes the calculations made to set the register default values This example dedi...

Страница 64: ...frames an Envelope frame as defined in IEEE802 3 can be of size 2000 bytes In this example dedicating up to 75 of the total bandwidth to the AV traffic we obtain hiLimitValue 2000 x 6144 12288000 loL...

Страница 65: ...Legacy Traffic I F The signals forming the Rx Legacy Traffic I F are defined in Table 5 3 All signals are synchronous to the Tri Mode Ethernet MAC receiver clock rx_clk which must always be qualified...

Страница 66: ...g within the core to allow for latency in the receive client After frame reception begins data is transferred on consecutive clock enabled cycles to the receive client until the frame is complete The...

Страница 67: ...trated in Figure 5 1 These have a greater flexibility than the standard address filter provided in the Tri Mode Ethernet MAC which must be disabled The MAC Header Filters include the ability to filter...

Страница 68: ...ligned with the legacy_rx_data_valid signal during frame reception Every bit within the legacy_rx_filter_match 7 0 bus will be asserted for frame reception in which the Frame Destination Address DA co...

Страница 69: ...compared to the initial 128 bits received in the Legacy Ethernet frame bit 0 is the first bit within the frame to be received Match Enable Register Each bit within this register refers to the same bit...

Страница 70: ...initial 48 bits of the received frame must exactly match the first 48 bits of the Match Pattern Register This example provides backwards compatibility with the Address Filters provided in the Tri Mod...

Страница 71: ...29 bits as used in this example of the received frame must exactly match the first 29 bits of the Match Pattern Register This functionality is useful for filtering across Multicast group Addresses X R...

Страница 72: ...the ability to filter across any bitwise match don t care pattern of the initial 128 bits of an Ethernet frame match combinations of Destination Address Length Type Field when no VLAN tag is present V...

Страница 73: ..._ prefix Error Free AV Traffic Reception Figure 7 7 illustrates the timing of a normal inbound frame transfer The AV client must be prepared to accept data at any time there is no buffering within the...

Страница 74: ...in which the av_rx_frame_bad is asserted in place of av_rx_frame_good indicates that this frame must be discarded by the AV client it was either received with errors or was not intended for the AV tra...

Страница 75: ...n The RTC is effectively a large counter which consists of a 32 bit nanoseconds field the unit of this field is 1 nanosecond and this field will count the duration of exactly one second then reset bac...

Страница 76: ...the smoother will be the overall RTC increment rate Xilinx recommends clocking the RTC logic at 125 MHz because this is a readily available clock source obtained from the transmit clock source of the...

Страница 77: ...d as illustrated The nanoseconds and sub nanoseconds fields can be considered to be concatenated together All RTC logic within the core is synchronous to the RTC Reference Clock rtc_clk X Ref Target F...

Страница 78: ...een reserved for the Increment Value the upper 6 bits of which overlap into the nanoseconds field For this reason the largest per cycle increment 1ns 2 6 64 ns The lowest clock period which is expecte...

Страница 79: ...for PTP messages This time stamping of packets is a key element of the tight timing synchronization across the AVB network wide RTC and these samples must be performed in hardware for accuracy The har...

Страница 80: ...ce the GMII exists only as an internal connection within the embedded block Therefore by sampling on the client interface we enable the Ethernet AVB Endpoint core to be connected to ANY Xilinx Tri Mod...

Страница 81: ...722 specification defines the avbtp_timestamp field This is derived by sampling the IEEE802 1 AS Real Time Clock and converting the low order time to nanoseconds From version 2 1 onwards this conversi...

Страница 82: ...82 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010 Chapter 8 Real Time Clock and Time Stamping...

Страница 83: ...The Tx PTP Packet Buffer is divided into eight identical buffer sections as illustrated Each section contains 256 bytes which are formatted as follows the first byte at address zero contains a frame...

Страница 84: ...TP frames have been sent and which are still queued Following transmission completion of each requested PTP frame a dedicated interrupt signal interrupt_ptp_tx will be generated by the core On the ass...

Страница 85: ...rgest PTP frame Should an illegally oversized PTP frame be received the first 252 bytes will be captured and stored other bytes will be lost The top four addresses of each buffer from address 0xFC to...

Страница 86: ...packet information X Ref Target Figure 9 2 Figure 9 2 Rx PTP Packet Buffer Rx PTP Packet Buffers Buffer Number Buffer Base Address 0 1 2 3 4 5 6 7 0x0000 0x0100 0x0200 0x0300 0x0400 0x0500 0x0600 0x0...

Страница 87: ...the following information is provided for reference only See the EDK documentation for further information The PLB interface defined by IBM can be complex and support many usage modes such as multipl...

Страница 88: ...arget Figure 10 1 Figure 10 1 Single Read Transaction PLB_RNW PLB_BE 0 7 PLB_size 0 3 PLB_type 0 2 PLB_abort PLB_ABus 0 31 PLB_PAValid SI_wait SI_addrAck PLB_wrDBus 0 31 SI_wrDAck SI_wrComp PLB_wrBurs...

Страница 89: ...cycle by asserting Sl_wait and delaying Sl_addrAck Wait states can be inserted in the Write sample by delaying the assertion of Sl_wrDAck X Ref Target Figure 10 2 Figure 10 2 Single Write Transaction...

Страница 90: ...e space each unique PLB address value references a single byte of data The variable PLB_base_address shown in Figure 10 3 and in the tables that follow represent the starting base address of the AVB c...

Страница 91: ...ated in Standard CORE Generator Format X Ref Target Figure 10 3 Figure 10 3 PLB Address Space of the Ethernet AVB Endpoint Core and Connected Tri Mode Ethernet MAC 0x0000 0x1800 0x1000 0x2800 0x2000 0...

Страница 92: ...fer Control Register PLB_base_address 0x2000 Bit no Default Access Description 7 0 0 WO tx_send_frame bits The Tx PTP Packet Buffer is split into 8 regions of 256 bytes Each of these can contain a sep...

Страница 93: ...P packet 31 12 0 RO Unused Note A read or a write to this register clears the interrupt_ptp_rx interrupt asserted after each successful PTP packet reception Table 10 3 Rx Filtering Control Register PL...

Страница 94: ...r for the nanoseconds field of the Real Time Clock used to force step changes into the counter When in PTP clock master mode this can be used to set the initial value following power up When in PTP cl...

Страница 95: ...this increment register is very fine in units of 1 1048576 1 220 fraction of one nanosecond Therefore the RTC increment rate can be adjusted to a very fine degree of accuracy This provides the follow...

Страница 96: ...is sampled RTC Interrupt Clear Register Table 10 13 describes the control register defined for the interrupt_ptp_timer signal the periodic interrupt signal which is raised by the Real Time Clock Tabl...

Страница 97: ...hin the Ethernet AVB Endpoint core A single bit can be written to in a single CPU transaction in order to reset just that particular function several to all bits can be written to in a single CPU tran...

Страница 98: ...O PTP Receiver logic reset When written with a 1 forces the PTP receiver logic of the core to be reset This is a subset of the full receiver path reset of bit 1 This reset does not affect PTP receiver...

Страница 99: ...bits in this register and all bits in the Match Pattern Ethernet frame bits 32 to 63 register For each bit logic 1 enables the match the corresponding bit in the Match Pattern will be compared logic...

Страница 100: ...er Guide UG170 for additional descriptions of these registers MAC Address Filter Registers The Address Filter optionally present in the Tri Mode Ethernet MAC LogiCORE IP solution must not used Instead...

Страница 101: ...s an MDIO register via the Ethernet MAC construct the address as follows MDIO register address PLB_base_address 0x6000 MDIO_ADDRESS 8 where MDIO_ADDRESS is a 10 bit binary address constructed from the...

Страница 102: ...102 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010 Chapter 10 Configuration and Status...

Страница 103: ...6 devices 2 for Spartan 6 devices 4 for all Spartan 3 devices I O Location Constraints No specific I O location constraints are required Placement Constraints No specific placement constraints are re...

Страница 104: ...lk or ref_clk then this constraint is unnecessary and can be removed The maximum supported frequency of host_clk as specified by the Tri Mode Ethernet MAC core is 125 MHz The following UCF syntax show...

Страница 105: ...ectly on the new clock domain many constraints are required and must not be removed These constraints are also present in the example design UCF delivered with the core Clock Domain Crossing Constrain...

Страница 106: ...toggle TO rx_clear_toggle_resync TIG INST top ptp_packet_buffer_inst rx_ptp_packet_buffer_inst rx_mac_logic_in st address TNM FFS rx_buf_addr INST top ptp_packet_buffer_inst rx_ptp_packet_buffer_inst...

Страница 107: ...avb_configuration_inst tx_cpu_reclock rd_toggle TNM FFS tx_rd_toggle INST top avb_configuration_inst tx_cpu_reclock resync_read_toggle data_sy nc TNM FFS resync_tx_read_toggle TIMESPEC ts_tx_rd_toggl...

Страница 108: ...TIG INST top rtc_inst rtc_configuration_inst rtc_cpu_reclock rd_toggle TNM FFS rtc_rd_toggle INST top rtc_inst rtc_configuration_inst rtc_cpu_reclock resync_read_togg le data_sync TNM FFS resync_rtc_r...

Страница 109: ...c_set_toggle TIMESPEC ts_pulse1div128sec_toggle FROM pulse1div128sec_toggle TO resync_set_toggle 8 ns DATAPATHONLY clock domain crossing constraints for MAC Host I F Logic INST top generic_host_if_ins...

Страница 110: ...INST top generic_host_if_inst resync_host_toggle data_sync TNM FFS resync_host_toggle TIMESPEC ts_host_toggle FROM host_toggle TO resync_host_toggle 8 ns DATAPATHONLY INST top generic_host_if_inst ho...

Страница 111: ...o the Xilinx Embedded Development Kit EDK environment When generated in this format the core is designed to interface to the XPS LocalLink Tri Mode Ethernet MAC xps_ll_temac Refer to Using the Xilinx...

Страница 112: ...t MAC Soft Core Tri Mode Ethernet MAC Core Generation When generating the Tri Mode Ethernet MAC TEMAC core in the CORE Generator software be sure that the following options are selected Management Int...

Страница 113: ...re 12 1 Figure 12 1 Connection to the Tri Mode Ethernet MAC Core without Ethernet Statistics tx_clk tx_clk_en tx_data 7 0 rx_clk rx_clk_en rx_data 7 0 rx_data_valid rx_frame_good rx_frame_bad host_opc...

Страница 114: ...nable as used with the TEMAC must always be connected to the tx_clk_en input of the Ethernet AVB Endpoint core The Ethernet receiver client clock domain must always be connected to the rx_clk input of...

Страница 115: ...ure 12 2 Figure 12 2 Connection to the Tri Mode Ethernet MAC and Ethernet Statistic Cores tx_clk tx_clk_en tx_data 7 0 rx_clk rx_clk_en rx_data 7 0 rx_frame_good rx_frame_bad host_opcode 1 0 host_addr...

Страница 116: ...C in the CORE Generator software be sure that the following options are selected Enable EMACs Enable only a single EMAC from the pair at this time Host Type Select Host Speed Select Tri speed Global B...

Страница 117: ...x_clk_en tx_data 7 0 rx_clk rx_clk_en rx_data 7 0 rx_data_valid rx_frame_good rx_frame_bad host_opcode 1 0 host_addr 9 0 host_wr_data 31 0 host_req host_miim_sel host_miim_rdy host_rd_data_mac 31 0 ho...

Страница 118: ...rx_data_valid host_opcode 1 0 host_addr 9 0 host_wr_data 31 0 host_req host_miim_sel host_miim_rdy host_rd_data_mac 31 0 hos_rd_data_stats 31 0 host_clk CLIENTEMAC0PAUSEREQ CLIENTEMAC0PAUSEVAL 15 0 TX...

Страница 119: ...MAC connect host_rd_data_stats 31 0 of the Ethernet AVB Endpoint core to the host_rd_data 31 0 port of the Ethernet Statistics core Virtex 6 FPGA Embedded Tri Mode Ethernet MAC The Ethernet AVB Endpoi...

Страница 120: ...onnection of the Ethernet AVB Endpoint Core into an Embedded Processor Sub system Microblaze BRAM xps_intc xps_uartlite lmb_bram_if_cntlr Ethernet AVB Endpoint TEMAC Custom AV logic Custom Legacy logi...

Страница 121: ...tom logic blocks must be manually translated into pcores using the standard pcore approach described in Xilinx Platform Studio documentation The standard EDK flow can then be implemented to build the...

Страница 122: ...the AVB software drivers can be assigned to this instance in the Microprocessor Software Specification mss file Using an ISE Software Top Level Project X Ref Target Figure 12 7 Figure 12 7 Connection...

Страница 123: ...e EDK tool set The main advantages of this implementation hierarchy are in terms of possible faster development turn around for synthesis implementation run time This is as a result that the EDK compo...

Страница 124: ...oduct or an Embedded Tri Mode Ethernet MAC available in certain Virtex devices The xps_ll_temac functionality remains identical for either MAC implementation The integration of the Ethernet AVB Endpoi...

Страница 125: ...ction of the Ethernet AVB Endpoint Core into an Embedded Processor Sub system Microblaze BRAM xps_intc xps_uartlite lmb_bram_if_cntlr Ethernet AVB Endpoint XPS_LL_TEMAC Custom AV logic PLB PLB AV traf...

Страница 126: ...mbedded processor should be configured to use the software drivers provided with the core see Chapter 13 Software Drivers Ethernet AVB Endpoint Connections Figure 12 8 illustrates the overall connecti...

Страница 127: ...tion X Ref Target Figure 12 9 Figure 12 9 Connection to the XPS LocalLink Tri Mode Ethernet MAC tx_clk tx_clk_enable tx_data 7 0 rx_clk rx_clk_enable rx_data 7 0 rx_data_valid rx_frame_good rx_frame_b...

Страница 128: ..._GMII_TX_CLK_0_pin PORT GMII_RXD_0 fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin PORT GMII_RX_DV_0 fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin PORT GMII_RX_ER_0 fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin PORT...

Страница 129: ...Mac02AvbRxFrameBad PORT legacy_tx_data Temac02AvbTxData PORT legacy_tx_data_valid Temac02AvbTxDataValid PORT legacy_tx_underrun Temac02AvbTxUnderrun PORT legacy_tx_ack Avb2Temac0TxAck PORT legacy_rx_...

Страница 130: ...then use the AVB feature in a processor based system AXI_Ethernet Configuration To ensure that AVB Audio Video frames can be sent received the AXI Ethernet MAC should be configured via software initi...

Страница 131: ...he comments can be viewed by Doxygen and detailed descriptions of all aspects of the software are available throughout the code This should allow customers to fully understand the operation of the pro...

Страница 132: ...ges Software System Integration The software drivers for the Ethernet AVB Endpoint core need to be run on an embedded processor In addition they require instantiation into the overall software project...

Страница 133: ...nt core generation When the core has been generated in the EDK pcore format the value of the PLB base address will be automatically configured by XPS Interrupt Service Routine Connections The Ethernet...

Страница 134: ...XAVB_MAC_TX_ENABLE_MASK XAVB_MAC_TX_VLAN_ENABLE_MASK Ethernet AVB Endpoint Setup This section describes the main elements that you may have to modify in order to operate the Ethernet AVB Endpoint soft...

Страница 135: ..._SOURCE_ADDRESS_EUI48_LOW 0xCCBBAA You can edit the defines above to be the Ethernet Source Address for the device and the example software then provides code that translates this address into an XAvb...

Страница 136: ...initialization is for the AVB drivers to be inactive After the Ethernet link has been established the drivers can be started using the following function call This will begin operation of the IEEE802...

Страница 137: ...sing the provided demonstration test bench For detailed information about the Standard CORE Generator example design see Chapter 15 Detailed Example Design Standard Format For detailed information abo...

Страница 138: ...Mentor Graphics ModelSim v 6 5c and Synopsys VCS and VCS MX 2009 12 X Ref Target Figure 14 1 Figure 14 1 Ethernet AVB Endpoint Example Design and Test Bench Example Design Top Level Ethernet AVB Endp...

Страница 139: ...tware_manuals htm 2 Create a new project 3 For project options select the following A Virtex 6 Virtex 5 Spartan 3 Spartan 3E Spartan 3A 3A DSP or Spartan 6 device to generate the default Ethernet AVB...

Страница 140: ...s on GUI page 1 so that Standard CORE Generator format is selected 9 Click Generate to deliver the core using the default options The default core and its supporting files including the example design...

Страница 141: ...Libraries compiled for your system See the Compiling Xilinx Simulation Libraries COMPXLIB in the Xilinx ISE Synthesis and Verification Design Guide and the Xilinx ISE Software Manuals and Help You can...

Страница 142: ...ulate_vcs sh Verilog only The simulator script compiles the gate level model and the demonstration test bench adds relevant signals to a wave window and then runs the simulation to completion You can...

Страница 143: ...nx CORE Generator software the purpose and contents of the provided scripts the contents of the example HDL wrappers and the operation of the demonstration test bench Please refer to Chapter 16 Detail...

Страница 144: ...ollowing tables project directory The project directory contains all the CORE Generator software project files Table 15 1 Project Directory Name Description project_dir component_name ngc Top level ne...

Страница 145: ...Directory Name Description project_dir component_name doc eth_avb_endpoint_ds677 pdf Ethernet AVB Endpoint Data Sheet eth_avb_endpoint_ug492 pdf Ethernet AVB Endpoint User Guide Back to Top Table 15...

Страница 146: ...ssor is required in a real system which provides stimulus to the PLB performing write and reads that initiate PTP frame transmission Back to Top Table 15 4 Example Design Directory Cont d Name Descrip...

Страница 147: ...notated SimPrim based model used for timing simulation routed sdf Timing information for simulation Back to Top Table 15 7 Simulation Directory Name Description project_dir component_name simulation d...

Страница 148: ...Description Table 15 9 Timing Directory Name Description project_dir component_name simulation timing simulate_mti do ModelSim macro file that compiles Verilog or VHDL sources and runs the timing simu...

Страница 149: ...form Studio drivers avb_v2_04_a examples The driver examples directory contains an application example using the low level driver files Table 15 10 Driver Data Directory Name Description project_dir c...

Страница 150: ...es required per single instance of the device driver xavb c Provides the top level function calls for the Ethernet AVB Endpoint level 1 device driver xavb_ptp_packets c Provides the functions which ar...

Страница 151: ...sis is performed on the routed design using trce 6 A bitstream is generated 7 Netgen runs on the routed design to generate a VHDL or Verilog netlist as appropriate for the Design Entry project setting...

Страница 152: ...ates the complete example design for the Ethernet AVB Endpoint Individual sub blocks are described in the following sections Note The example design is designed to allow the core in isolation to be te...

Страница 153: ...gacy frames transmitted are then looped back and received at the corresponding AV and Legacy receive client interfaces Two instances of an Ethernet Frame Checker block configured differently and conne...

Страница 154: ...ted frame are defined by generics Destination Address Source Address Length Type the VLAN field is optional Additionally the expected length of the Ethernet frame can also be set using a parameter The...

Страница 155: ...it then requests a follow up frame to be sent For any other PTP frame type no action is taken Reading from the PTP Tx Control Status register clears the interrupt PTP Receive Interrupt Service Routin...

Страница 156: ...ains the following The number of PTP frames transmitted and received The number of AV frames transmitted and received The number of legacy frames transmitted and received All transmitted frame statist...

Страница 157: ...llows a Functional Simulation to immediately use the new settings However because these modifications require logical changes the Implementation Scripts must be re run on the design before running a T...

Страница 158: ...d the wave window section headings are also numbered to match Figure 15 3 Further signals of interest may be added as desired The signals added to the Timing Simulation are a subset of the ones used i...

Страница 159: ...user defined project directory component name Core release notes file component name doc Product documentation MyProcessorIPLib pcores eth_avb_endpoint_v2_04_a core netlist and HDL for the pcore pcor...

Страница 160: ...minute changes and updates Table 16 1 Project Directory Name Description project_dir component_name ngc Top level netlist This is instantiated by the Verilog or VHDL example design component_name xco...

Страница 161: ...The driver data directory contains the data files for automatic integration into Platform Studio Table 16 3 Doc Directory Name Description project_dir component_name doc eth_avb_endpoint_ds677 pdf Eth...

Страница 162: ...rectory containing the software device drivers for the Ethernet AVB Endpoint core and associated supporting files Table 16 5 Driver Data Directory Name Description project_dir component_name MyProcess...

Страница 163: ...ion example using the low level driver files Table 16 7 Driver Data Directory Name Description project_dir component_name MyProcessorIPLib drivers avb_v2_04 data avb_v2_1_0 mdd Current MDD file used i...

Страница 164: ...n values required per single instance of the device driver xavb c Provides the top level function calls for the Ethernet AVB Endpoint level 1 device driver xavb_ptp_packets c Provides the functions wh...

Страница 165: ...into the Embedded Development Kit EDK You can import a generated Ethernet AVB Endpoint netlist into an EDK project by following the usual steps to import a black box IP See the Xilinx Platform Studio...

Страница 166: ...166 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010 Chapter 16 Detailed Example Design EDK format...

Страница 167: ...a RTC implementation which uses a 40 ns clock period as its clock source this is worst case Therefore the controlled frequency RTC will only be updated every 40ns Because the concept of a RTC is a co...

Страница 168: ...tamp sample is equal to the period of the RTC reference clock in this example 40 ns By using a high frequency RTC reference clock a high degree of accuracy can be obtained X Ref Target Figure A 1 Figu...

Страница 169: ...clock to the RTC reference clock domain When in the RTC clock domain the toggle signal is re clocked using the two synchronization flip flops illustrated After this an edge detection circuit is used t...

Страница 170: ...Accuracy X Ref Target Figure A 3 Figure A 3 Sampling Position Uncertainty TIMING CASE 1 MAC Tx Rx clock toggle RTC Reference Clock Q0 Q1 Q2 Take RTC Sample clock boundary MAC Tx Rx clock toggle RTC Re...

Страница 171: ...ows that the accuracy is variable For example The request for the 1st time stamp is made at 60 ns Because the time to the next RTC reference clock is 20 ns this will not violate the setup time for the...

Страница 172: ...The RTC is sampled 1 RTC reference clock period later as 240 resulting in an error of only 1 ns Hopefully these examples have illustrated that the timing uncertainty in the asynchronous sampling circu...

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