Xilinx LogiCORE 1000BASE-X, Руководство пользователя

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50 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 4: Designing with the Core
R
Design Guidelines
Generate the Core
Generate the core using the CORE Generator, as described in Chapter 3, “Generating and
Customizing the Core.”
Examine the Example Design Provided with the Core
Before implementing the core in your application, examine the example design provided
with the core to identify the steps that can be performed:
•
Edit the HDL top level of the example design file to change the clocking scheme, add
or remove IOBs as required, and replace the GMII IOB logic with user-specific
application logic (for example, an Ethernet MAC).
•
Synthesize the entire design.
The Xilinx Synthesis Tool (XST) script and Project file in the
/implement/vhdl
(or
/implement/verilog
) directory may be adapted to include any added user’s HDL
files.
•
Run the implement script in the
/implement
directory to create a top-level netlist for
the design.
The script may also run the Xilinx tools
map
,
par
, and
bitgen
to create a bitstream
that can be downloaded to a Xilinx device. SimPrim-based simulation models for the
entire design are also produced by the implement scripts.
•
Simulate the entire design using the demonstration test bench provided in
/test/vhdl (or /test/verilog)
as a template.
•
Download the bitstream to a target device.
Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core
in Your Application
Before implementing your application, examine the example design delivered with the
core for information about the following:
•
Instantiating the core from HDL
•
Connecting the physical-side interface of the core (RocketIO transceiver or TBI)
•
Deriving the clock management logic
It is expected that the block level module from the example design will be instantiated
directly into customer designs rather than the core netlist itself. The block level contains
the core and a completed physical interface.