Chapter 5: Development Flow
DPU IP Product Guide
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PG338 (v1.2) March 26, 2019
Configure DPU Parameters
You can configure the DPU IP as shown in Figure 21. The details about these parameters can be found
in Chapter 3: DPU Configuration.
Figure 21: Configure DPU
Connect DPU with a Processing System in the Xilinx SoC
No matter how many DPU cores are configured, there is only one slave interface in the DPU IP. Each
DPU core has three master interfaces, one for instruction fetch and the other two for data fetch. The
number of master interfaces in the DPU IP depends on the DPU_NUM parameter.
You can connect the DPU to a processing system (PS) with any kind of interconnections. You must
ensure the DPU can correctly access the DDR memory space. Generally, an AXI data transaction passes
an Interconnect IP, the delay of data transaction will increase. The delay of the data transmission
between the DPU and the Interconnect will reduce the DPU performance. Therefore, Xilinx®
recommends that each data fetch master interface in the DPU connects to the PS through a direct
connection rather than through an AXI Interconnect IP. The reference connection between the DPU and
PS in the Xilinx Ult™ MPSoC is shown as Figure 22.
