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AMS101 Evaluation Card User Guide
UG886 (v1.3) November 6, 2013
Chapter 3:
AMS101 Evaluation Hardware
The block diagram includes these six sub-blocks:
•
20-pin XADC header for interfacing to an FPGA base board
•
16-bit DAC analog signal source (Analog Devices DAC AD5065)
•
I/O level translators for the serial peripheral interface (SPI) to the DAC
(SN74LVC2T45DCT)
•
DAC reference amplifier buffer (AD8033)
•
Connector pins to bring in external positive and negative sources
•
3-way jumper pins to select DAC source or external source going to XADC header
Interfacing to the FPGA Base Board
The AMS101 evaluation card has a 20-pin header that allows it to be plugged into the
XADC header, which is now available on all Xilinx 7 series FPGA and Zynq-7000 SoC base
boards. The XADC header provides a means to connect the analog inputs of the XADC to
the AMS101 evaluation card circuitry as well as providing a reference, power, and DAC
control signals.
Figure 3-2
shows the pinout and signal names for the XADC header on the
FPGA base board.
As mentioned, the XADC header on the FPGA base board and the 20-pin header on the
AMS101 evaluation card are both keyed. To ensure correct connectivity, the keys must be
properly aligned between the AMS101 evaluation card and the XADC header. Pin 1 on the
XADC header on the FPGA base board needs to connect to Pin 1 of the 20-pin header on
the AMS101 evaluation card.
X-Ref Target - Figure 3-2
Figure 3-2:
XADC Header Pinout
V
P
A
GND
V
AUX0N
V
AU
X
8
P
A
GND
DXN
AV
DD
DGND
DIO
DIO
V
N
V
A
UX0P
A
GND
V
AU
X
8
N
DXP
V
REF
A
V_5V
VCC_2V5
DIO
DIO
V
P
V
N
A
GND
V
A
UX0P
V
A
UX0N
A
GND
VA
U
X
8
P
VA
U
X
8
N
A
GND
DXP
DXN
V
REF
AV
DD
A
V_5V
DGND
VCC_2V5
DIO
DIO
DIO
DIO
UG
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