Xilinx Alveo U200 Скачать руководство пользователя страница 13 | Manualshive

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Xilinx Alveo U200 Скачать руководство пользователя страница 13

In addition, the following code must be placed in the project XDC file to correctly configure the
MCS file.

# Bitstream Configuration

# ------------------------------------------------------------------------

set_property CONFIG_VOLTAGE 1.8 [current_design]

set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

set_property CONFIG_MODE SPIx4 [current_design]

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]

set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]

set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]

set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]

# ------------------------------------------------------------------------

Program the Alveo Card

After the MCS file is created, see the procedure in the "Programming the FPGA Device" chapter
in the Vivado Design Suite User Guide: Programming and Debugging (

) to connect to the

Alveo Data Center accelerator card using the hardware manager.

1. Select Add Configuration Device and select the mt25qu01g-spi-x1_x2_x4 part.

2. Right-click the target to select Program the Configuration Memory Device.

a. Select the MCS file target.

b. Select Configuration File Only.

c. Click OK.

3. After programming has completed, disconnect the card in the hardware manager, and

disconnect the USB cable from the Alveo accelerator card.

4. Perform a cold reboot on the host machine to complete the card update.

Chapter 1: Introduction

UG1289 (v1.1.1) November 20, 2019

Alveo U200 and U250 Accelerator Cards

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Содержание Alveo U200

Страница 1: ...Alveo U200 and U250 Accelerator Cards User Guide UG1289 v1 1 1 November 20 2019...

Страница 2: ...1 General updates Editorial updates only No technical content updates 10 31 2019 Version 1 1 All sections Updated to the Vitis unified software platform throughout 02 15 2019 Version 1 0 Initial Xilin...

Страница 3: ...iption 16 UltraScale FPGA 16 DDR4 DIMM Memory 16 Quad SPI Flash Memory 16 USB JTAG Interface 17 FT4232HQ USB UART Interface 17 PCI Express Endpoint 17 QSFP28 Module Connectors 18 I2C Bus 18 Status LED...

Страница 4: ...esources 23 Documentation Navigator and Design Hubs 23 References 23 Please Read Important Legal Notices 25 UG1289 v1 1 1 November 20 2019 www xilinx com Alveo U200 and U250 Accelerator Cards 4 Send F...

Страница 5: ...ing the Xilinx Virtex UltraScale technology These cards accelerate compute intensive applications such as machine learning data analytics video processing and more The Alveo U200 U250 Data Center acce...

Страница 6: ...card details in this user guide are provided to aid understanding of the card features If the cooling enclosure is removed from the card and the card is powered up external fan cooling airflow MUST b...

Страница 7: ...DIMM interface 64 bit ECC dual rank support x4 x8 UDIMM support PC4 2400 compatible C3 288 pin DIMM interface 64 bit ECC dual rank support x4 x8 UDIMM support PC4 2400 compatible C1 X23433 102419 Car...

Страница 8: ...Power management with system management bus SMBus voltage current and temperature monitoring Dynamic power sourcing based on external power supplied 65W PCIe slot functional with PCIe slot power only...

Страница 9: ...Humidity 10 to 90 non condensing Operating Voltage PCIe slot 12 VDC 3 3 VDC 3 3 VAUXDC External 12 VDC Design Flows The preferred optimal design flow for targeting the Alveo Data Center accelerator c...

Страница 10: ...upport XDC N A Programming the FPGA Vivado Hardware Manager Vivado Hardware Manager Notes 1 UltraFast Design Methodology Guide for the Vivado Design Suite UG949 2 Vivado Design Suite User Guide System...

Страница 11: ...ted the Alveo Data Center accelerator card from the Boards tab the following figures appear The RTL based project can now be created Figure 5 Alveo Data Center Accelerator U200 Card New Project Summar...

Страница 12: ...B JTAG This part contains a protected region with the factory base image at the 0x00000000 address space This base image points to the customer programmable region at a 0x01002000 address space offset...

Страница 13: ...y BITSTREAM CONFIG SPI_32BIT_ADDR Yes current_design Program the Alveo Card After the MCS file is created see the procedure in the Programming the FPGA Device chapter in the Vivado Design Suite User G...

Страница 14: ...the adapter by its bracket or edges only Avoid touching the printed circuit board or the connectors Put the adapter down only on an antistatic surface such as the bag supplied in your kit If you are...

Страница 15: ...master serial configuration mode The Quad SPI flash memory NOR device has a capacity of 1 Gb If the JTAG cable is plugged in QSPI configuration might not occur JTAG mode is always available independe...

Страница 16: ...rank DDR4 interfaces are available The card is populated with four socketed single rank Micron MTA18ASF2G72PZ 2G3B1IG 16GB DDR4 RDIMMs Each DDR4 DIMM is 72 bits wide 64 bits plus support for ECC The d...

Страница 17: ...tion is allowed at any time regardless of the FPGA mode pin settings consistent with the UltraScale Architecture Configuration User Guide UG570 For more details about the FT4232HQ device see the FTDI...

Страница 18: ...fications for the 28 Gb s QSFP at the SNIA Technology Affiliates website https www snia org sff specifications2 Each QSFP connector has its own clock generator QSFP0 clock Clock generator Silicon Labs...

Страница 19: ...Description DS1 RED POWER_GOOD DS2 BLUE DONE_0 DS3 ORANGE STATUS_LED0 DS4 YELLOW STATUS_LED1 DS5 GREEN STATUS_LED2 Card Power System Limited power system telemetry is available through the I2C IP I2C...

Страница 20: ...g Constraints UG903 for more information The Alveo accelerator card XDC files are available for download from their respective websites along with this user guide Appendix A Xilinx Design Constraints...

Страница 21: ...otechnical Commission IEC Electromagnetic Compatibility EN 55032 2015 Information Technology Equipment Radio Disturbance Characteristics Limits and Methods of Measurement EN 55024 2015 Information Tec...

Страница 22: ...rter Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end of life If you have purchased Xilinx branded electrical or electronic products in...

Страница 23: ...tart All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics which you can use to...

Страница 24: ...Architecture Configuration User Guide UG570 Vivado Design Suite User Guide Programming and Debugging UG908 Virtex UltraScale FPGA Data Sheet DC and AC Switching Characteristics DS923 UltraScale Archit...

Страница 25: ...the Materials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of Sale which can be viewed at https w...

Страница 26: ...Apple Inc used by permission by Khronos PCI PCIe and PCI Express are trademarks of PCI SIG and used under license AMBA AMBA Designer Arm ARM1176JZ S CoreSight Cortex PrimeCell Mali and MPCore are trad...

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