MAIN FEATURES OVERVIEW
1)
Analog Video Input Front End Interface
2)
Triple ADC with 12 - 140 MHz Sampling Rate
3)
Integrated line locked PLL generates pixel clock from HSYNC
4)
Integrated 5-bit pixel clock phase adjustment for precise sample timing control
5)
Integrated clamp with timing generator
6)
Integrated Brightness & Contrast controls
7)
Integrated precision voltage reference
8)
Compatible with VGA through SXGA RGB graphics signals, and component TV,
9)
DTV and HDTV
10)
Mid-Scale Clamping
11)
Fully Sync Processing
12)
Black and mid-level precision clamp and calibration*
13)
Input video mode status detection
14)
Digital Video Input Front End Interface
15)
ITU-R BT. 656 …… 8 bits/channel ....…………… 1 channel
16)
RGB 444 ………….. 8/10/12 bits/channel ....…..… 1/ 3 channel
17)
YCbCr 444 .…..…... 8/10/12 bits/ channel ….…… 1/ 3 channel
18)
YCbCr 422 .…..…... 8/10/12 bits/ channel ….…… 1/ 2 channel
19)
Multi-format digital input up to 200M Pixel/sec
20)
Video data input pins re-order function
21)
Input video mode status detection
22)
YCbCr Color format conversion (422 to 444)
23)
Color space conversion (YCbCr to RGB)
24)
Inverse Gamma Correcting (De-Gamma)
25)
Programmable Data Enable (DE) generator
26)
Programmable Vertical Sync (VS) generator
27)
Programmable Horizontal Sync (HS) generator
28)
Digital Audio Input Front End Interface
29)
I2S input interface Up to 8 channel 192k sample rate
30)
S/PDIF input interface
31)
IEC60958 PCM audio
32)
IEC61937 compressed audio
33)
Digital Data Link Engine
34)
HDMI 1.1/1.0
35)
HDCP 1.1/1.0 with external Key link through micro processor
36)
DVI 1.0
37)
Supports DTV/ HDTV resolutions: 480i/ 576i/ 480p/ 576p/ 720p/ 1080i/ 1080p
38)
Supports video optional formats: EIA/CEA-861-B
39)
Analog TMDS Interface
40)
TMDS data link up to 2.0G-bit/s each channel
41)
Including 3 data channel and 1 clock channel
42)
DDC link base on Micro-processor (suggest 8051uP)
43)
Hot Plug detection
44)
TMDS Clock Channel Plug detection
