WM8973-EV1M
w
Rev 1.0, February 2005
35
APPENDIX
EXTERNAL DSP CONNECTION TO THE WM8973-EV1B
The WM8973-EV1B evaluation board has been designed to allow it to be easily connected to
an external DSP platform with error free operation.
The following information is provided to ease the connection process and ensure that all
signals sent and received by the WM8973-EV1B are reliable and at the correct voltage
levels.
AUDIO INTERFACE CONNECTIONS
It is recommended that twisted pair (signal twisted with GND) or shielded wires are used to
make the audio interface connections between the DSP and WM8973-EV1B platforms. This
is to ensure that no interference or noise is picked up by the clocks or data lines, thus
reducing performance and reliability.
When the WM8973 is set in
Slave Mode
, the jumpers on header H1 should be removed,
disconnecting the digital input section of the evaluation board. The audio interface timing
and data signals from the DSP platform should then be connected as shown in Figure 25.
The signals should be connected to H1 and not to the header strips J15 and J21 running up
each side of the device. Connecting the signals to the output side of the level-shift IC (U4)
will cause drive contention between U4 and the DSP and could result in damage to either or
both devices. In most cases, the DSP supplies will be set around 3V for low power portable
applications. The inputs to the level-shift IC (74ALVC164245) have a TTL threshold (i.e.
Logic High = +2V(min); Logic Low = +0.8V(max)) and low input current requirements (i.e.
15uA max) allowing most DSPs to connect directly.
MCLK
GND
GND
GND
GND
DACDAT
DACLRC
BCLK
H1
Figure 25 Connections from DSP Platform
The digital inputs to the WM8973 have a CMOS threshold (i.e. Logic High (min) =
DBVDDx0.7; Logic Low (max) = DBVDDx0.3). These are met directly by the level shift IC
outputs.
The jumpers on H2 should also be removed, disconnecting the digital output section of the
WM8973 evaluation board. The ADCDAT data from the WM8973 should then be connected
to the DSP via pin 8 of header strip J15 and the GND connection should be taken from pin 4
of header strip J15.
The ADCDAT signal should be taken direct from the WM8973 digital output as the output
side of the level-shift IC (U4) from the WM8973 is pulled up to +5V which may overdrive and
cause damage to the DSP inputs. The digital output levels of the WM8973 are Logic High
(min) = DBVDDx0.9; Logic Low (max) = DBVDDx0.1 which should meet the input level
requirements of most DSPs running at +3V supplies. If the DSP is running with +5V supplies
then the connections to it should be made from the output side of the level-shift IC (U4),
connecting the signals as shown in Figure 26.
Содержание WM8973-EV1B
Страница 1: ...WM8973 EV1M Evaluation Board User Handbook Rev 1 0...
Страница 3: ...WM8973 EV1M w Rev 1 0 February 2005 3 EVALUATION SUPPORT 44 IMPORTANT NOTICE 45 ADDRESS 45...
Страница 21: ...WM8973 EV1M w Rev 1 0 February 2005 21 SCHEMATIC LAYOUT Figure 13 Functional Diagram...
Страница 22: ...WM8973 EV1M w Rev 1 0 February 2005 22 Figure 14 Digital Input...
Страница 23: ...WM8973 EV1M w Rev 1 0 February 2005 23 Figure 15 Software Control...
Страница 24: ...WM8973 EV1M w Rev 1 0 February 2005 24 Figure 16 Level Shift...
Страница 25: ...WM8973 EV1M w Rev 1 0 February 2005 25 Figure 17 Analogue Input...
Страница 26: ...WM8973 EV1M w Rev 1 0 February 2005 26 Figure 18 WM8973...
Страница 27: ...WM8973 EV1M w Rev 1 0 February 2005 27 Figure 19 Analogue Output...
Страница 28: ...WM8973 EV1M w Rev 1 0 February 2005 28 Figure 20 Power...
Страница 29: ...WM8973 EV1M w Rev 1 0 February 2005 29 WM8973 EV1B PCB LAYOUT Figure 21 Top Layer Silkscreen...
Страница 30: ...WM8973 EV1M w Rev 1 0 February 2005 30 Figure 22 Top Layer...
Страница 31: ...WM8973 EV1M w Rev 1 0 February 2005 31 Figure 23 Bottom Layer...
Страница 32: ...WM8973 EV1M w Rev 1 0 February 2005 32 Figure 24 Bottom Layer Silkscreen...
