082791 OPERATIONS MANUAL 2
BP/CX 3-26 CARDCAGES/MOTHERBOARDS
Electrical and Mechanical Specifications
Electrical
COMPONENT SIDE
CIRCUIT SIDE
PIN
SIGNAL
NAME
SIGNAL
FLOW DESCRIPTION PIN
SIGNAL
NAME
SIGNAL
FLOW DESCRIPTION
LOGIC 1
Vcc
In Logic
Power
(+5VDC) 2 Vcc In
Logic
Power
(+5VDC)
POWER 3
GND
In Logic
Ground
4
GND
In Logic
Ground
BUS
5
VBB#1/VBAT
In
Logic Bias #1/Bat Pwr
6
VBB#2/DCPD*
In
Logic Bias #2/Pwr Dwn
7 D3/A19 In/Out
8 D7/A23 In/Out
9 D2/A18 In/Out
10 D6/A22 In/Out
11 D1/A17 In/Out
12 D5/A21 In/Out
DATA BUS
13 D0/A16 In/Out
Data Bus/Address Ext
14 D4/A20 In/Out
Data Bus/Address Ext
15 A7 Out
16 A15 Out
17 A6 Out
18 A14 Out
19 A5 Out
20 A13 Out
21 A4 Out
22 A12 Out
23 A3 Out
24 A11 Out
25 A2 Out
26 A10 Out
27 A1 Out
28 A9 Out
ADDRESS
BUS
29 A0 Out
Address Bus
30 A8 Out
Address Bus
31
WR*
Out
Write to Memory or I/O
32
RD*
Out
Read Memory or I/O
33
IORQ*
Out
I/O Address Selection
34
MEMRQ*
Out
Memory Address Selection
35 IOEXP* In/Out
I/O
Expansion
36 MEMEX* In/Out
Memory
Expansion
37
REFRESH*
Out
Refresh Timing
38
MCSYNC*
Out
CPU Machine Cycle Sync.
39
STATUS 1*
Out
CPU Status
40
STATUS 0*
Out
CPU Status
41 BUSAK* Out
Bus
Acknowledge
42 BUSRQ*
In Bus
Request
43 INTAK* Out
Interrupt
Acknowledge 44 INTRQ*
In Interrupt
Request
45 WAITRQ* In Wait
Request
46 NMIRQ*
In Nonmaskable
Interrupt
47
SYSRESET* Out System
Reset
48 PBRESET* In Pushbutton
Reset
49
CLOCK*
Out
Clock from Processor
50
CNTRL*
In
AUX Timing
CONTROL
BUS
51
PCO*
Out
Priority Chain Out
52
PCI
In
Priority Chain In
53
AUX GND
In
AUX Ground
54
AUX GND
In
AUX Ground
AUXILIARY
POWER
BUS
55
AUX +V
In
AuX Positive (+12VDC)
56
AUX-V
In
AUX Negative (-12VDC)
* Low-level active indicator
Mechanical
Connector Spacing: 5/8” (0625”)
Mechanical Dimensions: See Included Drawings
Содержание BP3-26
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