Wersi CD 600, Инструкция по сборке

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AM 320-01-808
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4. CO1 (Co-Master)
The CPU 68B09E (IC 14) communicates with the master
with the help of a "2-Port-RAM", as is known from the
slaves 5L5. This means that the CPU is timed with SE and
SQ, the inverse E and 0 of the master. Switching over
between the master and co-master addresses or control
signals is done by IC 16, 18, 20, 22 (HC 157) and PAL (IC
6), while IC 15 (HCT245) and IC 21 (HC245) switch over
the data buses.
The RAM has a size of 64 kbyte and is in case of a power
failure - similar to the MST8 board - protected against data
loss. Since the CPU has an address size of 64 k only, but
has to manage 192 kbyte of data and program, a large
portion can be accessed to by banking. This is done by the
bank latch 1C7 (HC174) in combination with the PAL (IC
6).
256 bytes from the 32 k program area are for I&O (IC 1, IC
2). IC 3 (HC138) is responsible for decoding in the I/O
area.
The timer (IC 12) produces the necessary interrupts for the
system software and the clock for the ACIA (IC 4).
The ACIA is the serial interface of the organ and provides
or processes the serial data flow of the MIDI interface or
the R5232 interface.
The ADCO804 (IC 5) converts the voltage values coming
from CB 40 (volume control board) into digital values.
IC 10 (HCT574) and IC 11 (HC541) are responsible for the
operation of the rhythm control panel.
Via IC 9 (HCT541), data is transferred (DCS) to the drums
(DSP 160) or the potentiometer address is written into the
latch on CB4O (POTADR).