WIRELESS CONNECTIVITY & SENSORS
Evaluation board user manual
C
P CB
= Parasitic capacitance of PCB Parasitic capacitance of the PCB can vary depending on
design and track length. It can vary from 0.5 pF to 2 pF.
For the crystal
with load capacitance of 9pF and parasitic capacitance of 2 pF. The
value of C9 and C10 results in 12 pF which was also tested on the evauation board.
Depending on parasitic capacitance of Host PCB, a capacitance of 12 pF may be a good start-
ing value for C9 and C10.
Using standard firmware the external crystal is not needed. To enable use of
the LFXO a custom firmware is required.
Figure 9: LFXO mounting
3.5.6 NFC
Using standard firmware NFC is not supported. To enable use of the NFC a
custom firmware is required and an antenna and antenna matching network
needs to be connected to the corresponding pins. In case of using NFC func-
tion, the corresponding pins are connected to the CON3 through place holders
for matching circuitry to tune the NFC antenna.
3.5.7 Programming interface
The evaluation board provides a 2×10 pin connector to connect directly to a JTAG flash adapter
used for development. Please take care of the correct mounting of the flash adapter. The
recommended flash adapter is one of the "Segger J-Link" family.
Jumper JP6 will prevent the module from starting in debug mode when no flash adapter is
connected. To apply this, remove the flash adapter connection. Make sure a jumper at JP6 is
placed. Unplug and replug the USB connection of the device. Press the reset button on the
evaluation board.
Thyone-I, Proteus-III(-SPI), Setebos-I
21
Version 1.5, May 2023