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WM_PRJ_Q24NG_PTS_002-001 June
2006
Typical implementation:
VCC
VCC
SPI_IO
SPI_CLK
GPO or GPIO
SPI_EN
RST
Figure 4: Example of SPI Bus typical implementation
3.2.2.2
I
2
C
The I
2
C interface includes a CLK signal (SCL) and a DATA signal (SDA)
complying with a standard 96 kHz interface. The maximum transfer speed
is 400 kbits/s.
3.2.3
SPI Auxiliary bus
A second SPI Chip Enable (called SPI_AUX) can be used to add a SPI
peripheral to the Wireless CPU Q24NG.
3.2.4 Keyboard
interface
This interface provides 10 connections:
•
5 rows (ROW0 to ROW4),
•
5 columns (COL0 to COL4).
Scanning is digital, and the debouncing is performed in the Q24NG. No
discrete components like R, C (Resistor, Capacitor) are needed.
