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WM_PRJ_Q2686_PTS_001-010
June 30, 2009
Q2686 Wireless CPU
®
3.4
Serial interface
The Q2686 Wireless CPU
®
provide two SPI bus (i.e. for LCD, memories…). or an
I²C 2-wire interface..
3.4.1
SPI Bus
Both SPI bus interfaces include:
•
A CLK signal
•
An I/O signal
•
An I signal
•
A CS (Chip Select) signal complying with the standard SPI bus (any
GPIO).
•
An optional Load signal (only the SPIx-LOAD signal)
3.4.1.1
Characteristics
•
Master mode operation
•
The CS signal must be any GPIO
•
The LOAD signal (optional) is used for the word handling mode (only the
SPIx-LOAD signal)
•
SPI speed is from 102 kbit/s to 13 Mbit/s in master mode operation
•
3 or 4-wire interface(5-wire possible with the optional SPIx-LOAD signal)
•
SPI-mode configuration: 0 to 3 (for more details, refer to document.
•
1 to 16 bits data length
3.4.1.2
SPI configuration
Operation Maximum
Speed
SPI-
Mode
Duplex
3-wire
type
4-wire
type
5-wire type
Master 13
Mb/s 0,1,2,3 Half
SPIx-CLK;
SPIx-IO;
GPIOx as
CS
SPIx-
CLK;
SPIx-IO;
SPIx-I;
GPIOx as
CS
SPIx-CLK; SPIx-
IO; SPIx-I; GPIOx
as CS; SPIx-
LOAD (not
muxed in GPIO);
For the 3-wire configuration, SPIx-I/O is used as input and output.
For the 4-wire configuration, SPIx-I/O is used as output only, SPIx-I is used as input only.
For the 5-wire configuration, SPIx-I/O is used as output only, SPIx-I is used as input only. And the
dedicated SPIx-LOAD signal is used. It is an additional signal in more than a Chip Select (any other
GPIOx)