Although in most practical situations serial links have very good quality and thus have
very rare instances of transmission errors, host applications still have to make sure
there are application level error detection and recovery mechanisms in place.
6.5
Flow Control and Buffer Management
Figure 2 shows a typical set up for a host application that uses MUX feature. Buffers
that are involved in the MUX data flow are also included in the figure. Four channels
are used in this example.
Figure 2: MUX data flow
Gx64 APPLICATION NOTE
Individual channel flow control via MSC in the MUX mode is not as responsive as
hardware flow control used in the serial mode. As shown in Figure 2, individual
channel flow control (in Figure 2 flow control for DLC4 is shown) is applied at a higher
level (MUX layer) than the layer that hardware flow control operates. As a result, de-
asserting virtual RTS on the host application side will stop flow on the GR/GS64 side
slower than it will by hardware RTS signal. By the time the virtual RTS signal reaches
the upper layer of target side, some data could have already transmitted over the
serial link (e.g. from GR/GS64 UART IO buffer to Host UART IO buffer in Figure 2) and
some data could have travelled from DLC buffers to the UART IO buffer (e.g. from
DLC4 buffer to UART IO buffer on the GR/GS64 side in Figure 2). Data flow can not be
stopped at the UART IO buffer layer either because there could be data from other
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Ce document est la propriété exclusive de WAVECOM. Il ne peut être communiqué ou divulgué à des tiers sans son autorisation préalable
27.010 MUX Feature
Page: 15/24
