7-2
Schematic Diagram
7.2 Main Board
7.2.1 Chipset (Ulysse & Omega)
LDOs
interface
analog I/O
Memory interface
Serial
interface
PERMANT
F95/P
F95/A
1.8V
APPLY
ulysse digital core
2.0V
50mA
debug &
VR2
PERMANT
ON/OFF
LCDSYNC
reference
MCU
level shifter
F95/P
F95/P
interface
Power Supply
omega analog
misc
Omega interrupt
TWL3011GGMR
interface
ARM
Serial port
SIM
VR3
TSCYM
(1608)
LMK212BJ225MG-T
MCSI
interface
serial port
SIM
CODEC
BACK UP
Time
V/I
baseband
IrDA port
120mA
Debug
interface
Voiceband
Serial port
manegement
omega digital core
Power
manegement
JTAG &
2.85V
I/O
ON/OFF
load max
120mA
F95/P
CODEC
voiceband
control
interrrupt
2.85V
50mA
80mA
misc
VR2B
LDO
VR1
VR1B
Generic
F95/P
test
(1608)
Mwire
2.85V
Baseband
ulysse,omega I/O
F741529AGHHR
Keybd interface
on/off
Bat
OUT VOLTAGE
PERMANT
ulysse memory
TSP
VR2
UPR
UPR
20K
R510
C526
10u/10V
220K
R505
VBAT_2
(1608)
1u
C507
TP516
C519
100n
10u/10V
BACKUP_BATTERY
UPR
UPR
C521
R506
10K
VR2B
100n
C530
TP520
R504
10K
47u/4.0V
C588
EMK107BJ104KA-T
100n
C517
1n
C504
R508
510K
C531
10u/10V
C513
100n
VR1
VR2B
R519
120K
C500
UPR
R503
VR1
100p
0
TP502
TP501
R502
0
TP517
UPR
TP500
C527
10u/10V
VR1B
EMK107BJ104KA-T
100n
C528
H1
D1
VR2BOUT
E2
VR2IN
VR2OUT
E1
VR2SEL
D3
VR3OUT
H10
VREF
F4
VS1
B1
A1
VS2
UDR
UDX
J6
UEN
F5
UPR
C3
A3
VAUX
VBACKUP
J3
E5
VBAT
VCC1
K3
VCC2
D2
VCC3
G9
E4
VCHG
VCK
H6
K7
VDR
VDX
G6
G7
VFS
C1
VR1BOUT
VR1OUT
SRST5
A2
SVDD
K2
SWITCH
B7
TCK
A7
TDI
TDO
C7
J4
TDR
TEN
K4
TEST1
C8
TEST2
B8
TEST3
A9
B9
TEST4
F2
TESTRESETZ
A8
TMS
B6
TSCXM
A6
K6
K9
MCIBIAS
J8
MICIN
MICIP
K8
ONNOFF
D10
OSCAS
F1
PWON
B10
F3
REFGND
F6
RESPWRONZ
RPWON
A10
RTC_ALARM
D7
C4
SCLK3
SCLK5
B4
B2
SIO3
D4
SIO5
B3
SRST3
D5
D9
BULQP
D8
K10
BUZZOP
A4
CK13M
H3
COMP
F10
DAC
EARN
H8
H9
EARP
J1
FDBK
K1
GRND1
C2
GRND2
GRND3
G10
G1
IBIAS
ICTL
E3
INT1
F7
H4
INT2
C5
J9
BDLIM
E8
BDLIP
E7
E10
BDLQM
BDLQP
E9
H5
BDR
K5
BDX
BFSR
G5
BFSX
J5
BGTR1
G4
BGTR2
G3
BGTR3
G2
H2
BGTR4
BGTR5
J2
BULIM
C10
BULIP
C9
BULQM
OMEGA_VER2_0
U501
ADIN1
B5
ADIN2
A5
ADIN3
E6
D6
ADIN4_TSCXP
C6
ADIN5_TSCYP
AFC
F8
J7
AGNDA1
F9
APC
G8
AUXGND
H7
AUXI
J10
AUXON
AUXOP
15p
C503
CC5V
X501
C501
12p
100n
C512
C515
100n
LMK107BJ224KA-T(1608)
220n
C516
10u/10V
C525
VDDS12
N9
J10
VDDS13
VDDS14
P14
K3
VDDS15
K12
VDDS21
VDDS22
D10
A14
VDDS23
VDDS24
C3
H13
VDR
H12
VDX
H11
VFSRX
VBAT
TSPEN2
B14
C12
TSPEN3_NSCS2
TXIR_IRDA_X_A4
F1
F2
TX_IRDA
TX_MODEM
D2
VCLKRX
G11
VDD1
A13
P8
VDD2
F10
VDD3
J5
VDD4
VDDA1
G12
P12
VDDARM
VDDLMM1
B8
A3
VDDLMM2
VDDLMM3
M5
L6
VDDS11
B13
TSPACT1
TSPACT10_NWAIT
H10
K13
TSPACT11_MCLK
TSPACT2
B12
D11
TSPACT3
TSPACT4
B10
E9
TSPACT5
TSPACT6_NCS6
E8
E7
TSPACT7_CLKX_SPI
TSPACT8_NMREQ
C6
E6
TSPACT9_MAS1
TSPCLKX
E14
C14
TSPDI_I_O4
D14
TSPDO
TSPEN0
D13
D12
TSPEN1
D3
RX_MODEM
SCLK_INT1N
E3
C4
SDI_SDA
C1
SDO_INT10N
D1
SD_IRDA_CLKOUT_DSP
J11
SIM_CD_MAS0
J14
SIM_CLK
SIM_IO
J13
SIM_PWCTRL_I_O5
J12
SIM_RST
K14
G1
TCK
TCXOENE11
H2
TDI
TDO
H3
TMS
H1
TSPACT0
C13
NEMU0
G2
G4
NEMU1
L8
NFOE_X_A3
L9
NFWE_X_A0
NRESET_OUT_I_O7K11
NRESPWRON
G3
F4
NSCS0_SCL
NSCS1_X_A2
G5
D6
ON_OFF
OSC32K_INE10
A11
OSC32K_OUT
A10
RFEN_NOPC
RNW
N8
E4
RTS_MODEM_TOUT
F3
RXIR_IRDA_X_A1
RX_IRDA
E1
MCSI_CLK_I_O11
D9
D8
MCSI_FSYNCH_I_O12
MCSI_RXD_I_O10
B9
A9
MCSI_TXD_I_O9
A8
MCUDI
C8
MCUDO
MCUEN0
C7
MCUEN1_I_O8
B7
A7
MCUEN2_I_O13
K7
NBHE_I_O14
NBLE_I_O15
K8
NBSCAN
H4
P6
NCS0
NCS1
L7
P7
NCS2
NCS3
M7
B6
IT_WAKEUP_INT4N
I_O0_TPU_WAIT
J1
J3
I_O1_TPU_IDLE
I_O2_IRQ4
M4
M6
I_O3_SIM_RNW
KBC0_NFIQ
A6
KBC1_NIRQ
A5
KBC2_XDI_00
B5
KBC3_XDI_01
D5
E5
KBC4_XDI_02
KBR0_XDI_03
A4
B4
KBR1_XDI_04
KBR2_XDI_05
D4
B3
KBR3_XDI_06
KBR4_XDI_07
A2
LT_PWL
B1
GND10
L10
GND2
N6
M10
GND3
GND4
B2
L12
GND5
E12
GND6
P1
GND7
GND8
A12
J2
GND9
GNDA1
H14
B11
GNDA2
GNDARM
N11
P3
GNDLMM1
GNDLMM2
N7
C5
GNDLMM3
IDDQ
C9
DATA14
M14
L13
DATA15
DATA2
P10
N10
DATA3
DATA4
K10
P11
DATA5
M11
DATA6
L11
DATA7
DATA8
N12
P13
DATA9
DSR_MODEM_LPG
F5
H5
EN_LMM_PWR_X_IOSTRB
EXT_FIQ
D7
E13
EXT_IRQ
M9
FDP_NIACK
C10
GND1
BDR
F13
BDX
G13
F12
BFSR
F14
BFSX
C2
BU_PWT
CLK13M_OUT_START_BIT
L14
CLK32K_OUTC11
CLKTCXO
G14
M8
CS4_ADD22
CTS_MODEM_XF
E2
DATA0
P9
DATA1
K9
DATA10
N13
M13
DATA11
DATA12
M12
N14
DATA13
P4
ADD16
ADD17
K5
L5
ADD18
ADD19
N5
K2
ADD2
P5
ADD20
ADD21_CK16X_IRDA
K6
ADD3
K4
ADD4
L1
ADD5
L2
L3
ADD6
ADD7
M1
N1
ADD8
ADD9
M3
F11
BCLKR_ARMCLK
G10
BCLKX_I_O6
U500
ULYSSE_179BGA
J4
ADD0
ADD1
K1
M2
ADD10
ADD11
N2
P2
ADD12
ADD13
N3
L4
ADD14
ADD15
N4
12p
C502
510K
R512
VR3
0
R501
R513
100K
R500
0
10K
R507
TP503
100K
R509
TP518
BACKUP_BATTERY
20K
R511
C510
100n
U503
DG9411DL-T1
1
2
3
4
5
6
TP515
C518
TP514
DG9411DL-T1
1
2
3
4
5
6
(2012)
2.2u
MELODY_LED
MELODY_RST
RF_ENA
TDO
EN_BACKLIGHT
EN_ORANGE
EN_GREEN
EN_BLUE
U520
LCD_SUB_V1
SYN_EN
BSW
PDB
PRECHARGE
-BHE
MICIN
MICIP
EARN
EARP
A(17)
A(18)
A(19)
A(20)
A(21)
LCD_CS_MAIN
ON_OFF
LCD_CS_SUB
ON_OFF
RECEIVER_ON
LCD_MAIN_V1
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
D(7)
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
A(1:21)
PA_ON
TX_ON
BATT_ID
TEMP_LCD
AFC
PA_LEVEL
RXQN
RXQP
RXIN
RXIP
TXQN
TXQP
TXIN
TXIP
CLK
D(0:15)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
KBR(0:4)
KBC(0:4)
KBR(1)
KBR(2)
KBR(3)
KBR(4)
KBC(0)
KBC(1)
KBC(2)
KBC(3)
KBC(4)
13MHZ
CS2
RD
FWE
LCD_RES
WR
RTS
DEBUG_RX
RXD
LCD_SCL
LCD_SI
TDI
LCD_A(0)
DEBUG_TX
TXD
EAR_HOOK
A(22)
CTS
D(0)
DSR
FDP
JACK_DET
REED
KBR(0)
MELODY_IRQ
-BLE
CS0
CS1
TCK
DATA
TMS
BACKUP_BATTERY
DC_VOLT
13MHZ_OUT
ICTL
ON_OFF
END_ON_OFF
RPWRON
SIM_CLK
SIM_I-O
SIM_RST
SIM_VDD
Содержание GSM ST11
Страница 1: ...GSM PHONE SERVICE MANUAL MODEL ST11 ...
Страница 2: ...Rev 1 00 ...
Страница 6: ...1 2 Introduction Memo ...
Страница 15: ...3 4 Exploded View and Parts List 3 4 1 Exploded View 3 5 ...
Страница 41: ...Troubleshooting Memo 5 20 ...
Страница 42: ...6 Block Diagram 6 1 BB Block Diagram 6 1 ...
Страница 43: ...6 2 Block Diagram 6 2 RF Block Diagram ...
Страница 51: ...7 8 Schematic Diagram Memo ...
Страница 52: ...8 PCB Diagram 8 1 Main PCB 8 1 Top View ...
Страница 53: ...8 2 PCB Diagram Bottom View ...
Страница 60: ...9 7 Electrical Parts List Memo ...