Vizio Gallevia GV46LHDTV10A, Руководство по обслуживанию

Страница: 38 / 180

CONFIDENTIAL – DO NOT COPY Page 8-
7
File No. SG-0199
The two-wire protocol requires each slave device to be addressable by a 7-bit identification
number.
A two-wire data transfer consists of a stream of serially transmitted bytes formatted as shown
in the figure below. A transfer is initiated (START) by a high-to-low transition on MSTR_SDA
while MSTR_SCL is held high. A transfer is terminated by a STOP (a low-to-high transition on
MSTR_SDA while MSTR_SCL is held high) or by a START (to begin another transfer).
Figure 8-6 Two-Wire Protocol Data Transfer
Each transaction on the MSTR_SDA is in integer multiples of 8 bits (i.e. bytes).
The number of bytes that can be transmitted per transfer is unrestricted. Each byte is
transmitted with the most significant bit (MSB) first. After the eight data bits, the master
releases the MSTR_SDA line and the receiver asserts the MSTR_SDA line low to
acknowledge receipt of the data.
The master device generates the MSTR_SCL pulse during the acknowledge cycle. The
addressed receiver is obliged to acknowledge each byte that has been received.
The operation of Video Processor FLI8125
FLI8125 is another video processor designed by Genesis. In this product, we use FLI8125 to
process most of PIP source input and then output digital video signal to FLI8532.
Figure 8-7 FLI8125 System Block Diagram