4
To aide in interfacing to external equipment, the CLB-501B incorporates and auxiliary
header that provides 3.3VDC power, ground, and a buffered version of the pixel clock.
The buffered clock enables access to the reference clock without the risk of degradation of
the raw clock signal which could cause a malfunction. The raw (unbuffered) pixel clock is
also available on the header, but care should be taken in its use. The buffered clock is
sourced from the output (frame grabber) side of the breakout header.
All signals on the header utilize standard LVTTL levels. Care must be taken when
interfacing to the header to avoid damage to the internal components.
The CLB-501B incorporates high-speed (85MHz) interfaces and is compatible with any
“base” configuration camera. “Medium” configuration applications are supported using
two CLB-501B’s in parallel. The CLB-501B does not support the Camera Link “full”
configuration.
The latency (i.e. delay) of the video, control, and communication signals passing through
the CLB-501B is minimal. This is an important criteria in time-critical applications. See
Table 1.1 for the latency specifications.
CLB-501B also acts as a repeater and doubles the maximum separation between the
camera and the frame grabbers.
A front-panel link status indicator illuminates when the camera video signal is detected.
The front panel also includes a power indicator.
The CLB-501B is powered by an external wall plug-in power supply. A multi-nation
power supply is standard. Optionally, the CLB-501B is available with a locking-plug
power supply. The locking plug reduces the risk of accidental disconnection from the
rear-panel power jack. The CLB-501B is also available without power supply.
The CLB-501B DC power input is electrically isolated from the internal circuitry. This
feature ensures compatibility with user power systems.
