V1.0 Vig625M Motherboard Manual
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Adjust CPU FSB Frequency (MHz)
This item allows you to adjust the CPU FSB frequency.
Adjusted CPU Frequency (MHz)
It shows the adjusted CPU frequency (FSB x Ratio). Read-only.
Advance DRAM Configuration
Press <Enter> to enter the sub-menu.
DRAM Timing Mode
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to [Auto By SPD] enables DRAM timings
and the following related items to be determined by BIO S based on the
configurations on the SPD. Selecting [Manual] allows users to configure the
DRAM timings and the following related items manually.
CAS Latency (CL)
When the DRAM Timing Mode sets to [Manual], the field is adjustable. This
controls the CAS latency, which determines the timing delay (in clock cycles)
before SDRAM starts a read command after receiving it.
tRCD
When the DRAM Timing Mode sets to [Manual], the field is adjustable. When
DRAM is refreshed, both rows and columns are addressed separately. This setup
item allows you to determine the timing of the transition from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
tRP
When the DRAM Timing Mode sets to [Manual], the field is adjustable. This item
controls the number of cycles for Row Address Strobe (RAS) to be allowed to
precharge. If insufficient time is allowed for the RAS to accumulate its charge
before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain
data. This item applies only when synchronous DRAM is installed in the system.
tRAS
When the DRAM Timing Mode sets to [Manual], the field is adjustable. This setting
determines the time RAS takes to read from and write to a memory cell.
tRTP
When the DRAM Timing Mode sets to [Manual], the field is adjustable. Time
interval between a read and a precharge command.
tRFC
When the DRAM Timing Mode sets to [Manual], the field is adjustable. This setting
determines the time RFC takes to read from and write to a memory cell.
tWR
When the DRAM Timing Mode is set to [Manual], the field is adjustable. It
specifies the amount of delay (in clock cycles) that must elapse after the
completion of a valid write operation, before an active bank can be precharged.
