V1.0 VIG556M Motherboard Manual
50
DRAM Timing Control
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Clock/Timing Control
Performance Mode
Enabled
DRAM Timing Control
By SPD
x DRAM CAS Latency
2.5T
x RAS Active Time(tRAS)
6T
x RAS Precharge Time(tRP)
3T
x RAS to CAS Delay(tRCD)
3T
MA 1T/2T Select
Auto
Menu Level
►►
↑↓→←
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
F7: Optimized Defualts
Item Help
Figure 17:
DRAM Timing Control
Memory Timing
Allows the used to select the CAS latency time in HCLKs of 2, 2.5 or 3. The value is
set the factory depending on the DRAM installed. DO NOT change the values in this
field unless you have changed the DRAM or CPU.
