Vig550B Motherboard Manual – Ver 1.0
49
DRAM Timing Control
Figure 17:
DRAM Timing Control
Memory Timing
Allows the used to select the CAS latency time in HCLKs of 2, 2.5 or 3. The value is
set a the factory depending on the DRAM installed. DO NOT change the values in
this field unless you have changed the DRAM or CPU.
AGP & P2P Bridge Control
Figure 18:
AGP & P2P Bridge Control
