7
VT82885
Real Time Clock
VIA Technologies, Inc.
The 114 general purpose nonvolatile RAM
bytes are not dedicated to any special func-
tion within the VT82885. They can be used
by the processor program as nonvolatile
memory and are fully available during the
update cycles.
INTERRUPTS
The RTC plus RAM includes three separate,
fully automatic sources of interrupt for a pro-
cessor. The alarm interrupt can be pro-
grammed to occur at rates from once per
second to once per day. The peridoic inter-
rupt can be selected for rates from 500 ms
to 122
µ
s. The update-ended interrupt can
be used to indicate to the program that an
update cycle is complete. Each of these
independent interrupt conditions is de-
scribed in greater detail in other sections of
this text.
The processor program can select which
interrupts, if any, are going to be used.
Three bits in Register B enable the inter-
rupts. Writing a logic 1 to an interrupt-enable
bit permits that interrupt to be initi-ated when
the event occurs. A zero in an interrupt-
enable bit prohibits the IRQ# pin from being
asserted from the interrupt condition. If an
interrupt flag is already set when the
interrupt is enabled, IRQ# is im-mediately
set at an active level, although the interrupt
initiating the event may have occurred much
earlier. As a result, there are cases where
the program should clear such earlier
initiated interrupts before first ena-bling new
interrupts.
When an interrupt event occurs, the relating
flag bit is set to logic 1 in Register C. These
flag bits are set independent of the state of
the corresponding enable bit in Register B.
The flag bit can be used in a polling mode
without enabling the corresponding enable
bits. The interrupt flag bit is a status bit
which software can interrogate as neces-
sary. When the flag is set, an indication is
given to software that an interrupt event has
occurred since the flag bit was last read.;
however, care should be taken when using
the flag bits as they are cleared each time
Register C is read. Double latching is in-
cluded with Register C so that bits which are
set remain stable throughout the read cycle.
All bits which are set (high) are cleared when
read and new interrupts which are pending
during the read cycle are held until after the
cycle is completed. One, two, or three bits
can be set when reading Register C. Each
utilized flag bit should be examined when
read to ensure that no interrupts are lost.
The second flag bit usage method is with
fully enabled interrupts. When an interrupt
flag bit is set and the corresponding inter-
rupt enable bit is also set, the IRQ# pin is
asserted low. IRQ# is asserted as long as at
least one of three interrupt sources has its
flag and enable bits both set. The IRQF bit in
Register C is a one whenever the IRQ# pin
is being driven low. Determination that the
RTC initiated an interrupt is accom-plished
by reading Register C. A logic one in bit 7
(IRQF bit) indicates that one or more
interrupts have been initiated by the
VT82885. The act of reading Register C
clears all active flag bits and the IRQF bit.
OSCILLATOR CONTROL BITS
The VT82885’s internal oscillator can be
turned on and off as required. A pattern of
010 in bits 4 through 6 of Register A will turn
the oscillator on and enable the countdown
chain. A pattern of 11X will turn the oscilla-
tor on, but holds the countdown chain of the
oscillator in reset. All other combinations of
bits 4 through 6 keep the oscillator off.
SQUARE WAVE OUTPUT SELECTION
Thirteen of the 15 divider taps are made
available to a 1-of-15 selector, as shown in
the block diagram of Figure 1. The first
purpose of selecting a divider tap is to
generate a square wave output signal on the
SQW pin. The PS0-RS3 bits in Register A
establish the square wave output frequency.
These frequencies are listed in Table 1. The
SQW frequency selection shares its 1-of-15
selector with the periodic interrupt genera-
tor. Once the frequency is selected, the
output of the SQW pin can be turned on and
off under program control with the square
wave enable bit (SQWE)
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ#
pin to go to an active state from once every
500 ms to once every 122
µ
s. This function
is separate from the alarm interrupt which
can be output from once per second to once
per day. The periodic interrupt rate is se-
