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VIA 693/693A Twin Processor Mainboard
AWARD BIOS SETUP
4-17
CPU to PCI Write Buffer :
(Default Setting : Enabled)
When enabled, up to four Dwords of data can be written to the PCI bus without
interrupting the CPU. When disabled, a write buffer is not used and the CPU read
cycle will not be completed until the PCI bus signals is ready to receive the data.
PCI Dynamic Bursting :
(Default Setting : Enabled)
When
Enabled,
every write transaction goes to the write buffer. Burstable
transactions then burst on the PCI bus and nonburstable transactions don’t.
PCI Master 0 WS Write :
(Default Setting : Enabled)
When
Enabled,
writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction :
(Default Setting : Enabled)
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification
version 2.1.
PCI#2 Access #1 Retry :
(Default Setting : Disabled)
This item allows you enable/disable the PCI #2 Access #1 Retry.
AGP Master 1WS Write / Read
This implements a single delay when writing / reading to the AGP Bus. By default,
two-wait states are used by the system, allowing for greater stability.
Assign IRQ For VGA/USB
The system’s IRQ signals are limited and sometimes you may feel like to some
more IRQ signals for your add-on cards. The system BIOS allows you to disable
the IRQ which is supposed to be connected to VGA and USB ports. When you
have choose to disable the IRQ on VGA or USB port, the IRQ on the related IRQ
will be released and becomes available for other devices.
Before you can proceed with the change, please make sure that you do not have
USB and VGA adapter which will use the IRQ signal. Otherwise, your PC system
will become abnormal and the devices connected to these ports will be failed.