VIA Technologies NAB-7400, Руководство пользователя

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BIOS Setup
51
F
REQUENCY
/ V
OLTAGE
C
ONTROL
: Move
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
Menu Level
Item Help DRAM Clock [By SPD]
DRAM Timing [Auto By SPD]
Bank Interleave Disabled
Precharge to Active(Trp) 2T
Active to Precharge(Tras) 07T
Active to CMD(Trcd) 4T
REF to ACT/REF (Trfc) 15T
ACT(0) to ACT(1) (TRRD) 3T
SDRAM CAS Latency 2.5
Frequency / Voltage Control
Phoenix - AwardBIOS CMOS Setup Utility
Write to Read CMD (Twtr) [1T/2T]
Read to Precharge (Trtp) [3T]
[2T Command] DRAM Command Rate
RDSAIT mode
[Auto]
Write Recovery Time (Twr) [4T]
03
[Enabled]
[100MHz]
[ 6 X]
[0.25%]
RDSAIT selection
Auto Detect PCI Clk
CPU Clock
CPU Clock Ratio
Spread Spectrum
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency.
Settings: [By SPD, 100 MHz, 133 MHz, 166 MHz, 200MHz, 266MHz]
DRAM Timing
The value in this field depends on the memory modules installed in your
system. Changing the value from the factory setting is not recommended
unless you install new memory that has a different performance rating than
the original modules.
Settings: [Manual, Auto By SPD, Turbo, Ultra]
Read to Precharge (Trtp)
Settings: [2T, 3T]
Write to Read CMD (Twtr)
Settings: [1T/2T, 2T/3T]