VIA Technologies EPIA-SP, Руководство пользователя

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BIOS Setup
73
F
REQUENCY
/ V
OLTAGE
C
ONTROL
: Move
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
Menu Level
Item Help DRAM Clock [166 MHz]
DRAM Timing [Auto By SPD]
Bank Interleave Disabled
Precharge to Active(Trp) 4T
Active to Precharge(Tras) 9T
Active to CMD(Trcd) 4T
REF to ACT/REF to REF(Trfc) 15T
ACT(0) to ACT(1) (TRRD) 3T
SDRAM CAS Latency 2.5
Frequency / Voltage Control
Phoenix - AwardBIOS CMOS Setup Utility
Spread Spectrum [Enabled]
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency.
Settings: [66 MHz, 100 MHz, 133 MHz, 166 MHz, By SPD]
DRAM Timing
The value in this field depends on the memory modules installed in your
system. Changing the value from the factory setting is not recommended
unless you install new memory that has a different performance rating than
the original modules.
Settings: [Manual, By SPD]
SDRAM CAS Latency
This item is for setting the speed it takes for the memory module to
complete a command. Generally, a lower setting will improve the
performance of your system. However, if your system becomes less stable,
you should change it to a higher setting. This field is only available when
“DRAM Timing” is set to “Manual”.
Settings: [2, 2.5]