VESTEL MB120 DS, Руководство по обслуживанию

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Automatically programs and verifies data at selected page by an internal algorithm that automatically
times the program pulse widths (Any page to be programed should have page in the erased state first)6
P/N: PM1548 REV. 1.2, JUL. 02, 2010 MX25L8006E MX25L1606E
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Status Register Feature
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Electronic Identification
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JEDEC 1-byte manufacturer ID and 2-byte device ID
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RES command for 1-byte Device ID
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REMS commands for 1-byte manufacturer ID and 1-byte device ID
Hardware Features
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PACKAGE
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16-pin SOP (300mil), MX25L1606E only
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8-pin SOP (150mil)
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8-pin SOP (200mil)
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8-pin PDIP (300mil)
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8-land WSON (6x5mm)
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8-land USON (4x4mm)
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All Pb-free devices are RoHS Compliant
General Description
The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire
bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO).
Serial access to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page
basis, or word basis for erase command is executes on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The
status read command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features
section for more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
typical 100,000 program and erase cycles.