Vertex Standard VXA-710 SPIRIT, Руководство по обслуживанию, Страница: 8 / 40

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Circuit Description
signal within Q2023 . The 2nd IF signal then passes through
ceramic filter CF2001 (
SFECV10.7MS2
) to strip away
unwanted mixer products.
The filtered 2nd IF signal from ceramic filter CF2001 is
applied to the limiter amplifier section of Q2023 , which
removes amplitude variations in the 10.7 MHz IF before
detection of the speech by the detector (which includes
coil L2002 and capacitor C2061). Detected audio from
Q2023 is passed through the de-emphasis network R2074/
C2063, AF switch Q2022 ( HN1J02FU ), and high-pass fil-
ter Q2020-2 ( NJM2904V ). The processed audio signal from
Q2020-2 passes through the AF MUTEe gate Q2014
( DTC143ZE ) and the volume control to the audio power
amplifier Q2010 ( TDA7233D ), providing up to 0.4 Watts
to the headphone jack or 8
Ω
loudspeaker.
Squelch Control
When a signal is received, a DC squelch control voltage
appears at pin 15 of FM IF subsystem IC
Q2039 at a level
according to the received signal strength. This DC is ap-
plied to pin 13 of microprocessor
Q3026 ( LC87F52C8A ).
The DC squelch control voltage is compared with the SQL
threshold level by the microprocessor
Q3026 . If the DC
squelch control voltage is higher, pin 46 of Q3026 goes
high. This signal activates the AF MUTE gate Q2014
( DTC143ZE ), thus disabling the receiver audio.
If a signal strong enough to exceed the threshold level is
received the microprocessor stops scanning, if scanning
is engaged, and allows audio to pass through the AF
MUTE gate
Q2014 .
Transmit Signal Path
Speech input from the microphone is passed through mi-
crophone amplifier
Q3006-3 ( NJM2902V ), then applied
to the ALC amplifier Q3011 ( AN5123MS ). The amplified
speech signal is passed through the low-pass filter Q3006-
2 ( NJM2902V ) and high-pass filter Q3006-4 ( NJM2902V ),
where the signal is pre-emphasized and stripped of ex-
cessive high frequency components that might result in
over-deviation. The filtered speech signal is applied to
Q3013 ( M62364FP ) which adjusts the modulation level,
then deliver to the final amplifier Q1037 ( RD07MVS1 ) for
amplitude-modulation.
The carrier signal from the VCO Q1014 ( 2SC5555 ) passes
through buffer amplifier Q1017 ( 2SC5555 ) and TX/RX
switch
D1010
( HSU277 ). The signal from
D1010
is ampli-
fied by Q1029 ( 2SC3356 ) and Q1031 ( RD01MUS1 ), then
ultimately applied to the final amplifier Q1037
( RD07MVS1 ) which increases the signal level up to 5 watts
output power. The transmit signal then passes through
the antenna switch
D1016 ( RLS135 ), and is low-pass fil-
tered to suppress away harmonic spurious radiation be-
fore delivery to the antenna.
When using the optional headset, the SIDETONE port of
J2001 becomes “HIGH,” turning pin 18 of
Q3026 on; pin
56 of Q3026 then goes “HIGH,” routing a portion of the
speech to the AF power amplifier Q2010 as a monitor sig-
nal.
Automatic Transmit Power Control
RF power output from the final amplifier is sampled by
C1149/C1154 and is rectified by
D1021 ( HMS86WA ). The
resulting DC is fed through the Automatic Power Con-
troller
Q3012-2 ( NJU7018U ), thus allowing control of the
power output.
Transmit Inhibit
When the transmit PLL is unlocked, pin 7 of PLL chip
Q1013 ( MB15A01PFV1 ) goes to a logic “low.” The result-
ing DC “unlock” control voltage is turns off TX inhibit
switches
Q1016 ( 2SA1602A ), Q1018 ( UMW1 ), and Q1020
( DTA143EE ) to disable the supply voltage to transmitter
RF amplifiers, disabling the transmitter.
Spurious Suppression
Generation of spurious products by the transmitter is min-
imized by the fundamental carrier frequency being equal
to the final transmitting frequency. Additional harmonic
suppression is provided by a low-pass filter consisting of
L1030, L1035, and L1036 and C1147, C1153, C1155, C1159,
C1164, and C1167, resulting in more than 60 dB of har-
monic suppression prior to delivery of the RF signal to
the antenna.
PLL Frequency Synthesizer
The PLL circuitry consists of VCO Q1014 ( 2SC5555 ), VCO
buffers Q1017 and Q1021 (both 2SC5555 ), and PLL sub-
system IC Q1013 ( MB15A01PFV1 ), which contains a ref-
erence divider, serial-to-parallel data latch, programma-
ble divider, phase comparator, and charge pump.
Stability is maintained by a regulated 3.5 V supply via
Q1011 ( 2SB1132Q ) and Q1012 ( UMW1 ), which feeds the
PLL subsystem IC Q1013 ( MB15A01PFV1 ), as well as the
17.475 MHz PLL reference/2nd local oscillator X2001
( GS4613 ).
In the receive mode, VCO Q1014 oscillates between 133.65
and 199.4 MHz. The VCO output is buffered by
Q1017
and Q1021 , and applied to the prescaler section of Q1013 .
There the VCO signal is divided by 64 or 65, according to
a control signal from the data latch section of
Q1013 , be-
fore being applied to the programmable divider section
of
Q1013 . The data latch section of Q1013 also receives
serial dividing data from the microprocessor
Q3026
( LC87F72C8A ), which causes the pre-divided VCO sig-
nal to be further divided in the programmable divider
section, depending upon the desired receive frequency,
so as to produce a 5 kHz derivative of the current VCO
frequency.