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Interrupt Configuration

VSBC-8 Reference Manual 

Reference

 – 

47

Interrupt Configuration

The VSBC-8 has the standard complement of  PC type interrupts. Ten non-shared interrupts are
routed to the PC/104 bus, and up to four IRQ lines can be allocated as needed to PCI devices.

There are no interrupt configuration jumpers. All configuration is handled through CMOS setup.
The switches in the diagram below indicate the various CMOS Setup options. Closed switches
show factory default settings.

Note

If your design needs to use interrupt lines on the PC/104 bus, we recommend using
IRQ5, IRQ9, and/or IRQ10.

Figure 7. Interrupt Circuit Diagram

Содержание VSBC-8

Страница 1: ...Reference Reference Reference Reference Manual Manual Manual Manual VSBC 8 Pentium III Celeron based SBC with Ethernet Video Audio and Industrial I O...

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Страница 3: ...VSBC 8 Pentium III Celeron based SBC with Ethernet Video Audio and Industrial I O MVSBC 8...

Страница 4: ......

Страница 5: ...er releases Support Page The VSBC 8 Support Page at http www versalogic com private vsbc8support asp contains additional information and resources for this product including Reference Manual PDF forma...

Страница 6: ......

Страница 7: ...ice Although every effort has been made to ensure this document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warr...

Страница 8: ......

Страница 9: ...ting System Installation 8 Windows 98 newer versions 8 QNX Neutrino 8 Redhat Linux 7 X 8 DOS 8 3 Reference 9 Dimensions and Mounting 9 Hardware Assembly 10 Standoff Locations 10 External Connectors 11...

Страница 10: ...ace 28 Software Configuration 28 Video Resolutions 28 Video Output Connector 28 Flat Panel Display Connector 29 Compatible Flat Panel Displays 30 Ethernet Interface 31 BIOS Configuration 31 Status LED...

Страница 11: ...4 Jumper Configuration 44 External Connections 44 Counter Timer Registers 44 Operation 44 PC 104 Expansion Bus 45 Arranging the Stack 45 I O Configuration 45 Memory and I O Map 46 Memory Map 46 I O Ma...

Страница 12: ......

Страница 13: ...counter timers Two RS232 422 485 selectable ports Watchdog timer Vcc sensing reset circuit EBX Compliant 5 75 x 8 00 footprint UL and CE compliant Flash BIOS with OEM enhancements Latching I O connec...

Страница 14: ...ircuits and self resetting fuse on the 5V supply to the keyboard mouse USB 1 1 and Opto 22 I O ports VSBC 8 boards are subjected to a 48 hour burn in and 100 functional testing and are backed by a lim...

Страница 15: ...face 3 3V and 5V flat panel display support IDE Interface Two channels 40 pin 1 connectors Supports high speed IDE Type 4 and Ultra DMA drives Supports up to four IDE devices hard drives CD ROM etc Fl...

Страница 16: ...we can contact if we have questions Quantity of items being returned The model and serial number bar code of each item A description of the problem Steps you have taken to resolve or repeat the probl...

Страница 17: ...closed metallic anti static envelope Note The exterior coating on some metallic anti static bags is sufficiently conductive to cause excessive battery drain if the bag comes in contact with the botto...

Страница 18: ...optional DRAM MODULE Insert DRAM module into the DIMM socket Latch into place CABLES PERIPHERAL DEVICES Plug video adapter cable p n VL CBL 1007 into socket J1 and attach video monitor Plug keyboard a...

Страница 19: ...0 1 44 MB 3 5 Ide 2 Not installed Ext Floppy 1 Not installed Ide 3 Not installed 15MB Custom Configuration System BIOS Setup Custom Configuration C 2000 General Software Inc All rights reserved 64KB M...

Страница 20: ...rocedures as provided by the maker of the OS If special optimized hardware drivers are available for a particular operating system you can find these drivers or a link to the drivers at the VSBC 8 Pro...

Страница 21: ...s as shown in the diagram below Caution The single board computer must be supported at all eight mounting points to prevent excessive flexing when expansion modules are mated and demated Flex damage c...

Страница 22: ...ith four male female standoffs C threaded from the topside which also serve as mounting struts for the PC 104 stack The entire assembly can sit on a table top or it can be secured to a base plate When...

Страница 23: ...External Connectors VSBC 8 Reference Manual Reference 11 External Connectors CONNECTOR LOCATION DIAGRAM Figure 3 Connector Location Diagram...

Страница 24: ...ot 50 pin socket to 34 pin socket and 16 pin socket 42 34 825 6 175 J11 COM1 and COM2 Ports 3M 3421 7600 VersaLogic VL CBL 2001 1 foot 20 pin socket to two DB9F serial port connectors 23 2 025 6 600 J...

Страница 25: ...Jumper Block Locations VSBC 8 Reference Manual Reference 13 Jumper Block Locations Note Jumpers shown in as shipped configuration Figure 4 Jumper Block Location...

Страница 26: ...n this picture 6 MHz 44 V2 COM4 Configuration RS 485 RS 485 RS 232 RS 422 Endpoint Station Intermediate Station RS 232 22 V3 COM3 Configuration RS 485 RS 485 RS 232 RS 422 Endpoint Station Intermediat...

Страница 27: ...4x768 TFT Color Out Out Out In 14 1280x1024 Dual Scan STN Color Out Out Out Out 15 1024x600 Dual Scan STN Color 29 V7 Processor Side Bus Speed 66 MHz Selected by Processor out 18 V8 1 2 System BIOS Se...

Страница 28: ...DC pins and all three ground pins to prevent excess voltage drop Table 3 Main Power Connector Pinout J9 Pin Signal Name Description 1 5VDC Power Input 2 Ground Digital Ground 3 Ground Digital Ground 4...

Страница 29: ...irectly from the VSBC 8 and driving long RS 232 lines at high speed can increase power demand LITHIUM BATTERY Warning To prevent shorting premature failure or damage to the lithium battery do not plac...

Страница 30: ...0 pin CPUs have the chip dies mounted an a thin substrate If the substrate is flexed too far damage will occur to the die bonds Such damage will not be covered under the board warranty PROCESSOR SIDE...

Страница 31: ...nds 75 every 250 microsecond period Once the throttling percentage is initialized in the CMOS Setup it can be enabled and disabled by writing to the Throttle control bit in the VersaLogic Special Cont...

Страница 32: ...rase position Note The jumper should remain in position V5 1 2 for a full minute to properly erase the CMOS RAM contents Real Time Clock The VSBC features a year 2000 compliant battery backed 146818 c...

Страница 33: ...1 Align pin 1 on the DOC with pin 1 of socket U20 2 Push the DOC into the socket carefully until it is fully seated Warning The DOC can be permanently damaged if installed incorrectly When installing...

Страница 34: ...e CMOS Setup screen COM PORT CONFIGURATION There are no configuration jumpers for COM1 and COM2 since they only operate in RS 232 mode Jumper V3 is used to configure COM3 for RS 232 422 485 operation...

Страница 35: ...VersaLogic transition cable VL CBL 2001 Table 6 Connectors J11 J12 Serial Port Pinout COM1 J11 Pin COM2 J11 Pin COM3 J12 Pin COM4 J12 Pin RS 232 RS 422 RS 485 DB9 Pin 1 11 1 11 DCD 1 2 12 2 12 DSR 6...

Страница 36: ...VersaLogic transition cable VL CBL 2601 Table 7 LPT1 Parallel Port Pinout J15 Pin Centronics Signal Signal Direction DB25 Pin 1 Strobe Out 1 2 Auto feed Out 14 3 Data bit 1 In Out 2 4 Printer error In...

Страница 37: ...ignal from CPU 2 Ground Ground Ground 3 IDE7 DATA 7 Data bit 7 4 HD8 DATA 8 Data bit 8 5 HD6 DATA 6 Data bit 6 6 HD9 DATA 9 Data bit 9 7 HD5 DATA 5 Data bit 5 8 HD10 DATA 10 Data bit 10 9 HD4 DATA 4 D...

Страница 38: ...Ground 3 12 MSCLK Mouse Clock 5 13 MKPWR Protected 5V 4 14 KBDATA Keyboard Data 1 15 GND Ground 3 16 KBCLK Keyboard Clock 5 PROGRAMMABLE LED The Utility Connector J13 includes an output signal for att...

Страница 39: ...signal integrity The grounds in this connector should not be used to carry motor current Table 10 Floppy Disk Interface Connector Pinout J17 Pin Signal Name Function 1 Ground Ground 2 R LC Load Head 3...

Страница 40: ...color depths are available Table 11 Video Resolutions 4 MB Video RAM standard 640 x 480 16M colors 800 x 600 16M colors 1024 x 768 16M colors 1280 x 1024 64M colors 1600 x 1200 64K colors VIDEO OUTPUT...

Страница 41: ...P7 D7 LD0 UD0 G2 B7 SB1 SB3 B5 G3 LR2 LR1 UG1 J4 17 FP8 LD7 G3 G0 SB2 FG0 B3 UG1 UB1 J4 18 FP9 LD6 G4 G1 SB3 FG1 R4 UB1 LR1 J4 19 FP10 LD5 G5 G2 SB4 FG2 G4 UR2 LG1 J4 20 FP11 LD4 R0 G3 SB5 FG3 B4 UG2...

Страница 42: ...LQ084V1DG21 Sharp LQ10D344 Sharp LQ10D346 Sharp LQ10D367 Sharp LQ10D421 Sharp LQ9D161 Sharp LQ9D340 Sharp LQ10D131 Sharp LQ12S08 Sharp LQ12S31 Sharp LQ12S41 Sharp LQ64D142 Sharp LQ64D341 Sharp LQ64D34...

Страница 43: ...45 connector provide an indication of the Ethernet status as follows Green LED Link Activity ON Active Ethernet cable plugged into J2 No Tx Rx data activity OFF Cable not plugged into J2 Cable not plu...

Страница 44: ...me controls are provided An up pushbutton switch and a down pushbutton switch are normally connected between the appropriate pins on the connector and the ground reference Activation of a switch resul...

Страница 45: ...the watchdog NMI in al E0h or al 02h out E0h al Note The watchdog timer powers up and resets to a disabled state REFRESHING THE WATCHDOG If the watchdog timer is enabled software must periodically re...

Страница 46: ...Function 1 ADCH0 Channel 0 Analog Input 2 ADCH1 Channel 1 Analog Input 3 ADGND Analog Ground 4 ADCH2 Channel 2 Analog Input 5 ADCH3 Channel 3 Analog Input 6 ADGND Analog Ground 7 ADCH4 Channel 4 Analo...

Страница 47: ...the sampling aperture and or independent control of acquisition and conversion times The acquisition and start of conversion is controlled with two separate writes to the ACR register The first write...

Страница 48: ...sion underway data not yet available DONE 1 Analog input conversion has completed Valid data is available to be read from the ADCLO and ADCHI registers Done is reset to 0 when a new conversion is star...

Страница 49: ...n with the ADCLO register to read the complete 12 bit data word When reading data it is normal convention to read the ADCLO register first followed by the ADCHI register Table 19 ADCHI Bit Assignments...

Страница 50: ...onversion is complete as reported by the DONE bit in the ADCSTAT register the ADCLO register should be read first followed by the ADCHI register A word wide input instruction from the ADCLO register i...

Страница 51: ...ersion Data Step 0 004882813 Volts 0 to 10V Range 0 002441406 Volts 0 to 5V Range Sample values are shown in the table below Table 21 Two s Complement Data Format 5V Input Voltage 10V Input Voltage He...

Страница 52: ...in the table below Table 22 Binary Data Format 5V Input Voltage 10V Input Voltage Hex Decimal Comment 5 000000 10 000000 Out of range 4 998779 9 997559 0FFFh 4095 Maximum voltage 2 500000 5 000000 08...

Страница 53: ...compatible which provides a common industry software hardware interface Table 23 USB 1 1 Interface Connector J7 Pin Signal Name Function 1 USBPWR1 5V Protected 2 USBP00 Channel 0 Data 3 USBP01 Channe...

Страница 54: ...O 22 Module 15 18 GND Digital Ground 19 DIO1 OPTO 22 Module 14 20 GND Digital Ground 21 DIO2 OPTO 22 Module 13 22 GND Digital Ground 23 DIO3 OPTO 22 Module 12 24 GND Digital Ground 25 DIO4 OPTO 22 Mod...

Страница 55: ...I and DIRLO bits in the DCAS register see page 36 DIGITAL I O DATA PORTS DIOHI READ WRITE 00E7h or 1E7h via CMOS Setup D7 D6 D5 D4 D3 D2 D1 D0 DIO15 DIO14 DIO13 DIO12 DIO11 DIO10 DIO9 DIO8 DIOLO READ...

Страница 56: ...8 Pin Signal Name Function 1 OCTC3 CTC Channel 3 Output 2 GCTC3 CTC Chan 3 Gate Input 3 ICTC4 CTC Channel 4 Input 4 GND Digital Ground 5 OCTC4 CTC Channel 4 Output 6 GCTC4 CTC Chan 4 Gate Input 7 ICTC...

Страница 57: ...are stacked on top of the PC 104 Plus modules 16 bit modules first followed by 8 bit PC 104 modules Lastly non standard modules which lack feedthrough connectors should be assembled on top of the stac...

Страница 58: ...w Table 29 On Board I O Devices I O Device Standard I O Addresses Alternate I O Addresses Auxillary Counter Timer Channels 44h 47h Super I O COM 3 4 02Eh 02Fh Special Control Register 0E0h 1E0h Watchd...

Страница 59: ...our IRQ lines can be allocated as needed to PCI devices There are no interrupt configuration jumpers All configuration is handled through CMOS setup The switches in the diagram below indicate the vari...

Страница 60: ...e This bit is a read only bit D4 HDOGNMI Non Maskable Interrupt Enable Controls the generation of Non Maskable interrupts whenever the CPU temperature sensor detects an over temperature condition NMIE...

Страница 61: ...No Throttling VSBC 8d 1 VSBC 8b Throttling set at 37 5 VSBC 8e Note This bit is read only D1 D0 REV1 REV0 Revision Level These bits are represent the VSBC 8 circuit revision level REV1 REV0 Revision...

Страница 62: ...PGEN Battery Backed Static RAM Paging Enable Enables a 64K page frame from E0000h to EFFFFh Used to gain access to an optional Dallas Semiconductor Battery Backed Static RAM chip plugged into socket U...

Страница 63: ...ologies www Asiliant com 69030 A D Converter Maxim Integrated Products www maxim ic com Maxim 197 PC 104 Specification PC 104 Consortium www controlled com pc104 PC 104 Resource Guide CPU Chips Pentiu...

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