VersaLogic VL-MPEe-U2, Справочное руководство

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Interfaces and Connectors
General Purpose I/O (GPIO) Lines
The VL-MPEe-U2 provides twelve GPIO (digital I/O) lines that are independently configurable
as an input or output. GPIO inputs can be set for normal or inverted level, and optionally set to
generate an interrupt. GPIO outputs can be set to be normal HIGH or LOW state, or open drain.
There are 10K pull-up resistors to +3.3V on all GPIO lines.
VersaLogic provides a set of API calls for managing the GPIO lines. See Application
Programming Interface (API) for information.
Note:
Accesses to the GPIO functions are physically made using the Exar COM port
interface driver. Under Windows, this driver can only be opened by one application at
a time, so care should be taken that any systems wishing to use the serial port interface
and GPIO interface simultaneously synchronize their access to this COM port resource
through a single application.
GPIO C
ONNECTOR
Connector J3 provides a vertical 1x15 1 mm Pico-Clasp connector for the GPIO interface. The
VersaLogic VL-CBR-1502 cable assembly (consisting of the VL-CBR-1502A cable and the
VL-CBR-2004B paddleboard) attaches to connector J3 to provide a 20-pin screw terminal
interface for GPIO.
Table 6 shows the pinout of the J3 connector.
Table 6: J3 GPIO Connector Pinout
J3
Pin
Signal
Name
Function
1 UART_MPIO0 GPIO0
2 UART_MPIO1 GPIO1
3 UART_MPIO2 GPIO2
4 UART_MPIO3 GPIO3
5 GND Ground
6 UART_MPIO4 GPIO4
7 UART_MPIO5 GPIO5
8 UART_MPIO6 GPIO6
9 UART_MPIO7 GPIO7
10 GND Ground
11 UART_MPIO8 GPIO8
12 UART_MPIO9 GPIO9
13 UART_MPIO10 GPIO10
14 UART_MPIO11 GPIO11
15 GND * Ground
* Ground on standard products. Custom products can
be designed to make pin 15 UART_MPIO15.