Multi-purpose I/O
VL-EPU-3311 Reference Manual
37
User I/O Connector
The 40-pin user I/O connector incorporates the signals for the following:
Four USB ports
The GPIO (DIO) lines are 3.3 V Low-voltage TTL (LVTTL) compatible GPIOs capable of
sourcing/sinking up to 4 mA of current. Level shifting or current limiting is necessary when
connecting signals with different voltage rails.
Eight GPIO lines (these are functionally muxed with six timer I/O signals per FPGA
registers).There are eight timer signals and they share digital I/Os 16-9. The eight GPIO
lines on the paddleboard each have an alternate mode, accessible using the FPGA’s
AUXMOD1 register. Refer to the
EPU-3311 Programmer’s Reference Manual
for more
information on FPGA registers.
Three LEDs (two Ethernet link status LEDs and a programmable LED)
Two I
2
C signals (clock and data)
Push-button power switch
Push-button reset switch
Speaker output
This connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
Figure 19 shows the location and pin orientation of the user I/O connector.
Figure 19. Location and Pin Orientation of the User I/O Connector
