11.0 PDH Tools
PDH Menu
11.1 E1 Sa Bits & SSM QL (Clock Quality Level)
The Sa bits, or spare bits, are part of the NFAS (non-Frame Alignment Signal), which is sent at the beginning (time slot 0) of
each odd frame.
NFAS Word
1
2
3
4
5
6
7
8
E
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
E = Ebit (Far-end CRC block error indication)
A = Alarm (Remote Defect Indication)
San = Sa bits
The Sa bits have multiple applications, including point-to point serial communications or messaging. One of their applications is to
carry the Synchronization Signaling Message (SSM), which notifies the far end of the Clock Quality Level (QL) being used to
generate the E1 signal and whether it could be used as a timing source for other signals. The SSM is a repetitive four bit code.
The test set allows monitoring of all Sa bits simultaneously. Users can manually edit/encode each of the Sa TX fields by tapping
on the TX fields and using the keypad to enter any 8-bit sequence.
The SSM functionality is available for PCM31C, PCM30C, and PCM30 framing modes. When SSM is turned ON by selecting an
Sa channel, users can select pre-encoded 4-bit codes to transmit in the selected channel. The SSM code is repeated
continuously (displayed as an 8-bit word). If an invalid SSM QL sequence is manually entered, the test set will decode the first
four bits.
By default, the SSM selection field is set to OFF (no TX encoding or RX decoding).
If SSM = SaN (N=4-8), users will be able to use the TX "Sync QL" field pull-down to encode the desired Quality Level.
The default encoding is still "Do not use for Sync 1111"
Selecting a Sync QL value for the TX will update the affected Sa Bits TX field
Editing the affected Sa Bit Field will update the encoding label shown in Sync QL field
Sync Quality Level Values
RXT-3900 e-Manual D07-00-111P Rev A00
Содержание RXT3900
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