Doc. No: Unex-QSG-21-001
18/27
A printed version of this document is an uncontrolled copy
© 2021 Unex Technology Corporation – Company Confidential
8.1.2.3.
Tamper Detection (Optional)
Figure 14: Tamper input (J5)
Table 11: Tamper functions (J5)
Pin
Symbol
I/O
Level (V)
Description
J5.1
VDD_3V3
O
3.3
3.3V power to tamper switch
J5.2
TAMPER
I
-
Tamper signal. Active LOW.
J5.3
GND
G
-
Ground
J5.4
Reserved
-
-
Reserved. Leave open if not used.
J5.5
Reserved
-
-
Reserved. Leave open if not used.
The tamper detection function will be supported by project base. It is disabled by default.
J5 consists of 1.5mm pitch PTHs (Plated Through Holes) reserved for tamper detection
function. For connecting the tamper signal, tamper signal wires can be soldered directly
into PTHs. (Wires with JST 5P-SZN 1.5mm pitch board-in connector can be handled more
easily when soldering.)
Pulling the tamper detection pin to ground will trigger a tamper event, indicating that
the enclosure of the system has been opened without proper authorization.
The tamper detection mechanism is part of the FIPS 140-2 Level 3 security
requirements. The tamper detection itself is carried out entirely in HW. On SW level, there
is only an API that allows enabling the tamper detection mechanism. Calling this API will
move tamper HW state from the testing mode to the production mode. Once called, it
cannot move back to the testing mode.
The trigger mode of tamper detection signal can be selected with the DIP switch SW3.2.
TAMPER
J5.2
1
2
3
