SARA-N2 series - System Integration Manual
UBX-17005143 - R06
Design-in
Page 48 of 82
2.6.2
Secondary asynchronous serial interface (Secondary UART)
2.6.2.1
Guidelines for Secondary UART circuit design
The Secondary UART interface is provided on the GPIO1 pin and can be used for diagnostic, to collect
trace logs.
A suitable application circuit can be the one illustrated in
, where direct external access is
provided for diagnostic purpose by means of Test-Points made available on the application board for
GPIO1 and V_INT lines.
scaling
SARA-N2 series
(DCE)
16
GPIO1
GND
TestPoint
4
V_INT
TestPoint
Figure 26: UART AUX interface application circuit providing direct external access for diagnostic purpose
The circuit with a 1.8 V application processor should be implemented as described in
scaling
TxD
Application Processor
(1.8V DTE)
SARA-N2 series
(DCE)
16
GPIO1
GND
GND
0 ohm TestPoint
4
V_INT
TestPoint
Figure 27: UART AUX interface application circuit connecting a 1.8 V application processor
If a 3.3 V application processor is used, then it is recommended to connect the 1.8 V auxiliary UART
interface of the module by means of appropriate unidirectional voltage translators using the module
V_INT output as 1.8 V supply for the voltage translators on the module side, as described in
4
V_INT
TxD
Application Processor
(3.3V DTE)
GND
SARA-N2 series
(DCE)
16
GPIO1
GND
1V8
B
A
GND
U1
VCCB
VCCA
Unidirectional
Voltage Translator
C1
C2
3V3
DIR
VCC
0 ohm TP
TP
Figure 28: UART AUX interface application circuit connecting a 3.3 V application processor
Reference
Description
Part Number - Manufacturer
C1, C2
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
U1
Unidirectional Voltage Translator
SN74LVC1T45 - Texas Instruments
Table 22: Component for UART AUX interface application circuit connecting a 3.3 V application processor
☞
It is recommended to provide a direct access to the GPIO1 pin by means of accessible testpoints
for diagnostic purpose
☞
ESD sensitivity rating of auxiliary UART pins is 1 kV (Human Body Model according to JESD22-
A114). Higher protection level could be required if the lines are externally accessible on the
application board. Higher protection level can be achieved by mounting an ESD protection (e.g.
EPCOS CA05P4S14THSG varistor array) close to accessible points.